Released
PM7329
S/UNI-APEX-1K800
Packet/ATM Traffic Manager and Switch
FEATURES
• ATM (fixed length cell) and packet/
frame traffic manager and switch.
• 128 line ports, 4 WAN ports, and a
high speed microprocessor port. Any
port to any port switching for 1024
independent connections.
• Manages up to 256 Kbyte cell (16
Mbyte) data buffer and 4 Mbyte
context memory shared over all ports.
• Configurable progressive throttling of
buffer consumption, with memory
reservation under high consumption.
Performs EFCI marking for ABR
support.
• Buffer congestion controlled via Partial
Packet Discard, Early Packet Discard
(PPD/EPD). Cell at a time discard also
supported.
• For frame/packet flows:
•
via packet-contiguous queuing and
scheduling.
•
Error indication in AAL5 EOM trailer
(set by SAR or classifier) can invoke
errored packet discard, thereby
eliminating need for packet buffers
in external devices.
• Traffic queuing algorithm is highly
configurable on a per connection, per
class, and per port basis.
• Configurable scheduling of 4 classes
of service on every port, with rate
shaping available for the 4 WAN ports.
Configurable traffic parameters
enabling a mix of CBR, VBR, GFR,
and UBR classes.
• Configurable OAM cell queuing and
special handling on all ports.
• VPI/VCI header mapping.
• Supports 700 Mb/s ingress traffic and
700 Mb/s egress traffic aggregated
across all ports.
• Low power 3.3/ 2.5 V CMOS.
• Standard 5-pin P1149 JTAG port.
• 352-ball SBGA, 35 mm x 35 mm.
BUS INTERFACES
• 8/16 bit, 52 MHz UTOPIA L2 bus.
• Line side:
Enhanced UTOPIA Tx master
supports 128 ports. Rx master
supports 32 ports.
•
Or single port slave.
• WAN side:
•
•
•
Master (with optional cell length
expansion) supports 4 Tx or Rx
ports.
Or single port slave.
MICROPROCESSOR INTERFACE
• 66 MHz, 32 bit address/data bus
capable of single or burst access to
internal registers and cell buffers.
• Supports cell/packet transfer to/from
any port, with CRC32 and CRC10
calculation supported in hardware.
Supports external wire speed HDLC
processor, SAR, and flow classifier
BLOCK DIAGRAM
CMAB[18:17]
CMD[33:0]
CMA[18:0]
CMP[1:0]
CMRWB
Ctrl Lines
AD[31:0]
Processor
Interface
SSRAM Interface
LRCLK
LRPA
LRSX
LRSOP
LRDAT[15:0]
LRPRTY
LRENB
LRADR[5:0]
CMCEB
Loop Rx
Any-PHY
Que Management &
Scheduling
Loop Tx
Any-PHY
LTCLK
LTPA
LTSX
LTSOP
LTDAT[15:0]
LTPRTY
LTENB
LTADR[7:0]
WRCLK
WRPA
WRSX
WRSOP
WRDAT[15:0]
WRPRTY
WRENB
WRADR[2:0]
WAN Rx
Any-PHY
SDRAM Interface
JTAG Test
Access Port
WAN Tx
Any-PHY
WTCLK
WTPA
WTSX
WTSOP
WTDAT[15:0]
WTPRTY
WTENB
WTADR[2:0]
CBCSB
CBRASB
CBCASB
SYSCLK
CBA[11:0]
CBBS[1:0]
PMC-2010038 (r3)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
CBDQM[1:0]
CBDQ[31:0]
CBRWEB
TRSTB
TDO
RSTB
TMS
TCK
TDI
OE
© Copyright PMC-Sierra, Inc. 2001
PMC [ PMC-SIERRA, INC ]
