RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
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FEATURES
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Single-chip multi-channel HDLC controller with a 66 MHz, 32 bit Peripheral
Component Interconnect (PCI) Revision 2.1 bus for configuration, monitoring
and transfer of packet data, with an on-chip DMA controller with scatter/
gather capabilities.
Supports up to 256 bi-directional HDLC channels assigned to a maximum of
32 H-MVIP digital telephony buses at 2.048 Mbps per link. The links are
grouped into 4 logical groups of 8 links. A common clock and a type 0 frame
pulse is shared among links in each logical group. The number of time-slots
assigned to an HDLC channel is programmable from 1 to 32.
Supports up to 256 bi-directional HDLC channels assigned to a maximum of
8 H-MVIP digital telephony buses at 8.192 Mbps per link. The links share a
common clock and a type 0 frame pulse. The number of time-slots assigned
to an HDLC channel is programmable from 1 to 128.
Supports up to 256 bi-directional HDLC channels assigned to a maximum of
32 channelised T1/J1 or E1 links. The number of time-slots assigned to an
HDLC channel is programmable from 1 to 24 (for T1/J1) and from 1 to 31 (for
E1).
Supports up to 32 bi-directional HDLC channels each assigned to an
unchannelised arbitrary rate link, subject to a maximum aggregate link clock
rate of 64 MHz in each direction. Channels assigned to links 0 to 2 support a
clock rate of up to 51.84 MHz. Channels assigned to links 3 to 31 support a
clock rate of up to 10 MHz.
Supports three bi-directional HDLC channels each assigned to an
unchannelised arbitrary rate link of up to 51.84 MHz when SYSCLK is running
at 45 MHz.
Supports a mix of up to 32 channelised, unchannelised and H-MVIP links,
subject to the constraint of a maximum of 256 channels and a maximum
aggregate link clock rate of 64 MHz in each direction.
Links configured for channelised T1/J1/E1 or unchannelised operation
support the gapped-clock method for determining time-slots which is
backwards compatible with the FREEDM-8 and FREEDM-32 devices.
For each channel, the HDLC receiver supports programmable flag sequence
detection, bit de-stuffing and frame check sequence validation. The receiver
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PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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PMC [ PMC-SIERRA, INC ]
