RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
Figure 22 – TAP Controller Finite State Machine
TRSTB=0
Test-Logic-Reset
1
0
1
Run-Test-Idle
0
1
Capture-DR
0
Shift-DR
1
Exit1-DR
0
Pause-DR
1
0
Exit2-DR
1
Update-DR
1
0
0
0
0
1
Select-DR-Scan
0
1
Capture-IR
0
Shift-IR
1
Exit1-IR
0
Pause-IR
1
Exit2-IR
1
Update-IR
1
0
0
0
1
1
Select-IR-Scan
0
1
All transitions dependent on input TMS
Test-Logic-Reset
The test logic reset state is used to disable the TAP logic when the device is in
normal mode operation. The state is entered asynchronously by asserting input,
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
283
PMC [ PMC-SIERRA, INC ]
