RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
The timing relationship of the transmit data clock (TMVCK[n]), data (TD[m],
where 8n£m£8n+7) and frame pulse (TFPB[n]) signals of a link configured for
2.048 Mbps H-MVIP operation with a type 0 frame pulse is shown in Figure 26.
The FREEDM-32P256 samples TFPB[n] low on the falling edge of the
corresponding TMVCK[n] and references this point as the start of the next frame.
The FREEDM-32P256 updates the data provided on TD[m] on every second
falling edge of the corresponding TMVCK[n] as indicated for bit 2 (B2) of time-
slot 0 (TS 0) in Figure 26. The first bit of the next frame is updated on TD[n] on
the falling TMVCK[n] clock edge for which TFPB[n] is also sampled low. B1 is
the most significant bit and B8 is the least significant bit of each octet. Time-
slots that are not provisioned to belong to any channel (PROV bit in the
corresponding word of the transmit channel provision RAM in the TCAS256
block set low) transmits the contents of the Idle Fill Time-slot Data register.
Figure 26 – Transmit 2.048 Mbps H-MVIP Link Timing
TM VC K[n]
(4 MHz)
TFPB[n]
TD[m ]
B8
TS 31
B1
B2
B3
B4
TS 0
B5
B6
B7
B8
B1
TS 1
13.3 Receive non H-MVIP Link Timing
The timing relationship of the receive clock (RCLK[n]) and data (RD[n]) signals of
an unchannelised link is shown in Figure 27. The receive data is viewed as a
contiguous serial stream. There is no concept of time-slots in an unchannelised
link. Every eight bits are grouped together into a byte with arbitrary alignment.
The first bit received (B1 in Figure 27) is deemed the most significant bit of an
octet. The last bit received (B8) is deemed the least significant bit. Bits that are
to be processed by the FREEDM-32P256 are clocked in on the rising edge of
RCLK[n]. Bits that should be ignored (X in Figure 27) are squelched by holding
RCLK[n] quiescent. In Figure 27, the quiescent period is shown to be a low level
on RCLK[n]. A high level, effected by extending the high phase of the previous
valid bit, is also acceptable. Selection of bits for processing is arbitrary and is
not subject to any byte alignment nor frame boundary considerations.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
289
PMC [ PMC-SIERRA, INC ]
