RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
Figure 45 – Receive Data Timing (Non H-MVIP Mode)
RCLK[n]
tS
RD
RD[n]
tH
RD
Figure 46 – BERT Input Timing
TBCLK
tS
TBD
TBD
tH
TBD
Table 36 – FREEDM-32P256 Link Output (Figure 47 to Figure 50)
Symbol
Description
TCLK[31:0] Frequency (See Note 4)
TCLK[31:0] Frequency (See Note 5)
TCLK[2:0] Frequency (See Note 6)
TCLK[31:3] Frequency (See Note 6)
TCLK[31:0] Duty Cycle
TMVCK[3:0] Frequency (See Note 7)
TMVCK[3:0] Duty Cycle
TMV8DC Frequency (See Note 8)
TMV8DC Duty Cycle
TMV8FPC Frequency (See Note 9)
TMV8FPC Duty Cycle
40
4.092
40
16.368
40
4.092
40
Min
1.542
2.046
Max
1.546
2.050
51.84
10
60
4.100
60
16.400
60
4.100
60
Units
MHz
MHz
MHz
MHz
%
MHz
%
MHz
%
MHz
%
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA,INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
309
PMC [ PMC-SIERRA, INC ]
