RELEASED
DATA SHEET
PMC-2010333
ISSUE 3
PM7382 FREEDM-32P256
FRAME ENGINE AND DATA LINK MANAGER 32P256
Although a STATUS+RPDR only totals to 17 bits, each queue entry is a dword,
i.e. 32 bits. When the RMAC256 block writes a STATUS+RPDR to the ready
queue, it sets the remaining 7 bits in the third byte to zero and the fourth byte is
unmodified.
Figure 8 – RPDRR Queue Operation
Rx Packet Descriptor Reference Ready Queue
RP DRRQ _START _ADDR
RPDR RQ _RE AD_ADDR
RPD - 16 bytes
ST AT US + RPDR
ST AT US + RPDR
Bit 31
Bit 0
buffer
-packet M
RPDRRQ_W RITE_ADDR
ST AT US + RPDR
RPD - 16 bytes
buffer
-packet N
RPD - 16 bytes
buffer
-start of
packet O
RPD - 16 bytes
buffer
-m iddle of
packet O
RPD - 16 bytes
buffer
-end of
packet O
RP DRRQ _EN D_ADDR
Receive Channel Descriptor Reference Table
On a per-channel basis, the RMAC256 caches information such as the current
DMA information in a Receive Channel Descriptor Reference (RCDR) Table.
The RMAC256 can process 256 channels and stores three dwords of
information per channel. This information is cached internally in order to
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52
PMC [ PMC-SIERRA, INC ]
