RELEASED
DATASHEET
PMC-2010336
ISSUE 1
PM7383 FREEDM-32A256
FRAME ENGINE AND DATA LINK MANAGER 32A256
Register 0x108 : RCAS Framing Bit Threshold
Bit
Bit 15
to
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Type
Function
Unused
Default
XXXH
FTHRES[6]
FTHRES[5]
FTHRES[4]
FTHRES[3]
FTHRES[2]
FTHRES[1]
FTHRES[0]
0
1
0
0
1
0
1
This register contains the threshold used by the clock activity monitor to detect
for framing bits/bytes.
FTHRES[6:0]:
The framing bit threshold bits (FTHRES[6:0]) contains the threshold used by
the clock activity monitor to detect for the presence of framing bits. A counter
in the clock activity monitor of each receive link increments on each rising
edge of SYSCLK and is cleared, when the BSYNC bit of that link is set low,
by each rising edge of the corresponding RCLK[n]. When the BSYNC bit of
that link is set high, the counter is cleared at every fourth rising edge of the
corresponding RCLK[n]. When the counter exceeds the threshold given by
FTHRES[6:0], a framing bit/byte has been detected.
FTHRES[6:0] should be set as a function of the SYSCLK period and the
expected gapping width of RCLK[n] during data bits and during framing
bits/bytes. Legal range of FTHRESH[6:0] is ‘b0000001 to ‘b1111110.
Note: For operation with T1/J1 links and SYSCLK = 45 MHz, FTHRESH[6:0]
should be set to ‘b0100101’. The default value of this register reflects this
mode of operation.
PROPRIETARY AND CONFIDENTIAL
98
PMC [ PMC-SIERRA, INC ]
