RELEASED
DATASHEET
PMC-2010336
ISSUE 1
PM7383 FREEDM-32A256
FRAME ENGINE AND DATA LINK MANAGER 32A256
8.8.2 Line Interface
There are 32 identical line interface blocks in the TCAS256. Each line interface
block contains 2 sub-blocks; one supporting channelised T1/J1/E1 streams and
the other H-MVIP streams. Based on configuration, only one of the sub-blocks
are active at one time; the other is held reset. Each sub-block contains a bit
counter, an 8-bit shift register and a holding register. Each sub-block performs
parallel to serial conversion. Whenever the shift register is updated, a request for
service is sent to the priority encoder block. When acknowledged by the priority
encoder, the line interface would respond by writing the data into the holding
register in the active sub-block.
To support H-MVIP links, each line interface block contains a time-slot counter.
The time-slot counter is incremented each time the holding register is updated.
When a frame pulse occurs, the time-slot counter is cleared to indicate that the
next byte belongs to the first time-slot.
To support non H-MVIP channelised links, each line interface block contains a
time-slot counter and a clock activity monitor. The time-slot counter is
incremented each time the shift register is updated. The clock activity monitor is
a counter that increments at the system clock (SYSCLK) rate and is cleared by a
rising edge of the transmit clock (TCLK[n]). A framing bit (T1/J1) or a framing
byte (E1) is detected when the counter reaches a programmable threshold, at
which point, the bit and time-slot counters are initialised to indicate that the next
bit sampled is the most significant bit of the first time-slot. For unchannelised
links, the time-slot counter and the clock activity monitor are held reset.
8.8.3 Priority Encoder
The priority encoder monitors the line interfaces for requests and synchronises
them to the SYSCLK timing domain. Requests are serviced on a fixed priority
scheme where highest to lowest priority is assigned from line interface TD[0] to
line interface TD[31]. Thus, simultaneous requests from line interface TD[m] will
be serviced ahead of line interface TD[n], if m < n. The priority encoder selects
the request from the link with the highest priority for service. When there are no
pending requests, the priority encoder generates an idle cycle. In addition, once
every fourth SYSCLK cycle, the priority encoder inserts a null cycle where no
requests are serviced. This cycle is used by the channel assigner downstream
for CBI accesses to the channel provision RAM.
PROPRIETARY AND CONFIDENTIAL
63
PMC [ PMC-SIERRA, INC ]
