PM7384 FREEDM-84P672
DATA SHEET
PMC-1990445
ISSUE 5
FRAME ENGINE AND DATA LINK MANAGER 84P672
17
FREEDM-84P672 TIMING CHARACTERISTICS
(T
A
= -40°C to +85°C, V
DD3.3
= 3.0 to 3.6 V, V
DD2.5
= 2.3 to 2.7 V)
Table 45 – Clocks and SBI Frame Pulse (Figure 35)
Symbol
Description
REFCLK Frequency
REFCLK Duty Cycle
FASTCLK Frequency (51.84 MHz)
FASTCLK Frequency (44.928 MHz)
FASTCLK Frequency (66 MHz)
FASTCLK Duty Cycle
SYSCLK Frequency
SYSCLK Duty Cycle
TS
C1FP
TH
C1FP
TP
C1FPOUT
C1FP Set-Up Time to REFCLK
C1FP Hold Time to REFCLK
REFCLK to C1FPOUT Valid
Min
19.44
-50 ppm
40
51.84
-50 ppm
44.928
-50 ppm
66
-50 ppm
40
45
-50 ppm
40
4
1
2
Max
19.44
+50 ppm
60
51.84
+50 ppm
44.928
+50 ppm
66
+50 ppm
60
45
+50 ppm
60
Units
MHz
%
MHz
MHz
MHz
%
MHz
%
ns
ns
20
ns
Notes on Input Timing:
1. When a set-up time is specified between an input and a clock, the set-up
time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4
Volt point of the clock.
2. When a hold time is specified between an input and a clock, the hold time is
the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt
point of the input.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
336
PMC [ PMC-SIERRA, INC ]
