Preliminary
PM7388
FREEDM 336A1024
Frame Engine and Datalink Manager
FEATURES
• Single-chip multi-channel packet
processor supporting line rate
throughput transfers of packet sizes
from 40 to 9.6 Kbytes, for up to an
aggregate of 336 T1s, 252 E1s, or 12
DS-3s.
• Provides simultaneous support of
PPP, Frame Relay, Multilink-PPP and
Multilink-Frame Relay protocols.
Alternative protocols supported via
HDLC termination and full packet store
of the data within the HDLC structure.
configurable on a per multilink bundle.
Optionally full packet transfers are
supported on a per bundle basis.
• Supports up to 168 multilink bundles
with up to 12 member links per bundle.
These bundles are composed of
independent HDLC channels.
• Support for up to 100 ms of intra
bundle skew in the receive direction
when supporting the minimum.
fragment size.
• Support for PPP header compression
as per RFC 1661.
• Link Control protocol packets are
identified by the PID as control
protocols and will be forwarded to the
Any-PHY interface.
FRAME RELAY
• Link layer address lookup can be
performed based on HDLC channel
and 10 bit DLCI for HDLC channels
supporting Frame Relay protocols.
• The lookup algorithm can support a
maximum of 16 K connection
identifiers (CIs) amongst multilink FR
bundles. The connection identifiers
are ignored in singlelink FR channels.
• Control frames are identified and
forwarded to Any-PHY interface.
• 12 bit sequence numbers supported.
• FECN, BECN, and DE ingress
processing as per FRF.12.
MULTILINK PPP AND FRAME
RELAY BUNDLES
• Capable of supporting fragment sizes
from 1 to 9.6 Kbytes.
• Support for 3 egress fragmentation
sizes (128, 256, and 512 bytes)
PPP
• Support for 16 COS levels in
accordance with RFC 2686.
• Either 12 bit or 24 bit sequence
number, with short and long fragment
header formats, is supported.
BLOCK DIAGRAM
TCLK[11:0]
TD[11:0]
BCLK
AD[31:0]
ADSB
CSB
WR
BURSTB
BLAST
READYB
BTERMB
WRDONEB
INTHIB
INTLOB
BUSPOL
RSTB
PMCTEST
SCAN_EN
DLLTEST
SYSCLK
TDO
TDI
TCK
TMS
TRSTB
DDLL-
140
ACIFP
CIFPOUT
ADATA[7:0]
ADP
APL
AV5
AJUST_REQ
Insert
SBI
(INSBI-
336)
Transmit
Channel
Assigner
(TCAS-12)
JTAG
Microprocessor I/F (BUMP2)
Tx ANY-PHY
I/F (TAPI-12)
Egress
Queue
Manager
(EQM-12)
Tx
Fragment
Builder
(TFRAG)
SRAM
Controller
(SRAMC)
Tx HDLC
Processor /
Partial Packet
Buffer
(THDL-12)
TXCLK
TXADDR[15:0]
TPA
TXDATA[15:0]
TXPRTY
TRDY
TSX
TEOP
TMOD
TERR
CCDAT[35:0]
CCADD[17:0]
CCWEB
CCSELB
CCBSELB[1:0]
CBDAT[47:0]
CBADD[12:0]
CBWEB
CBCSB
CBRASB
CBCASB
CBBS[1:0]
RXCLK
RXADDR[3:0]
RPA
RENB
RXDATA[15:0]
RXPRTY
RVAL
RSX
RSOP
REOP
RMOD
RERR
Performance
Monitor
(PM-12)
REFCLK
Rx HDLC
Processor /
Partial Packet
Buffer
(RHDL-12)
CB DRAM
Controller
(CB_DRAMC)
DDATA[7:0]
DDP
DPL
DV5
DC1FP
Extract
SBI
(EXSBI-
336)
Receive
Channel
Assigner
(RCAS-12)
Rx
Fragment
Builder
(RFRAG)
Frame
Builder
(FRMBLD)
Ingress
Queue
Manager
(EQM-12)
Rx ANY-PHY
I/F
(RAPI-12)
RS DRAM
Controller
(RS_DRAMC)
RSDAT[31:0]
RSADD[12:0]
RSWEB
RSCSB
RSRASB
RSCASB
RSBS[1:0]
DQM
RCLK[11:0]
RD[11:0]
Data
Control
PMC-1991475 (p2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
Copyright PMC-Sierra, Inc. 2001
PMC [ PMC-SIERRA, INC ]
