STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
FE
LA
- internal FIFO empty status
- state of the LINK ACTIVE software flag
Figure 38 shows the timing of interrupts, the state of the FIFO, and the state of
the Data Link relative the input data sequence. The cause of each interrupt and
the processing required at each point is described in the following paragraphs.
The actual interrupt signal, INTB, is active low and will be the inverse of the INT
signal shown in figure 16. Also in this example, the programmable fill level set
point is set at 8 bytes by writing this value into the INTC[6:0] bits of the RDLC
Interrupt Control register.
At points 1 and 5 the first flag after all ones or abort is detected. A dummy byte
is written in the FIFO, FE goes low, and an interrupt goes active. When the
interrupt is detected by the processor it reads the dummy byte, the FIFO
becomes empty, and the interrupt is removed. The LINK ACTIVE (LA) software
flag is set to logic 1.
At points 2 and 6 the last byte of a packet is detected and interrupt goes high.
When the interrupt is detected by the processor, it reads the data and status
registers until the FIFO becomes empty. The interrupt is removed as soon as
the RDLC Status register is read, since the FIFO fill level of 8 bytes has not been
exceeded. It is possible to store many packets in the FIFO and empty the FIFO
when the FIFO fill level is exceeded. In either case the processor should use
this interrupt to count the number of packets written into the FIFO. The packet
count or a software time-out can be used as a signal to empty the FIFO.
At point 3 the FIFO fill level of 8 bytes is exceeded and interrupt goes high.
When the interrupt is detected by the processor it must read the data and status
registers until the FIFO becomes empty and the interrupt is removed.
At points 4 or 7 an abort character is detected, a dummy byte is written into the
FIFO, and interrupt goes high. When the interrupt is detected by the processor it
must read the data and status registers until the FIFO becomes empty and the
interrupt is removed. The LINK ACTIVE software flag is cleared.
12.6 T1 Automatic Performance Report Format
Table 16
- Performance Report Message Structure and contents
Octet No. Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1
1
2
3
4
FLAG
SAPI
C/R EA
EA
TEI
CONTROL
PROPRIETARY AND CONFIDENTIAL
200
PMC [ PMC-SIERRA, INC ]
