STANDARD PRODUCT
PM8315 TEMUX
DATASHEET
PMC-1981125
ISSUE 7
HIGH DENSITY T1/E1 FRAMER WITH
INTEGRATED VT/TU MAPPER AND M13 MUX
Figure 39
- T1/E1 Line Loopback
CTCLK*
TRANSMITTER
T1-XBAS/E1-TRAN
TOPS
ED[1:28]
ESIF
Egress
BasicTransmitter:
Timing Options
Frame Generation,
Alarm Insertion,
Signaling
ECLK[1:28]/EFP[1:28]/
Interface
ESIG[1:28]
TJAT
TxCLK[1:28]
TxD[1:28]
CEFP*
Digital Jitter
Attenuator
Trunk Conditioning
CECLK*
Line Coding
FRAM
CICLK*
CIFP*
Framer/
Li ne Loopback
ELST
Elastic
Store
Slip Buffer
RAM
T1/E1-FRMR
Framer:
ID[1:28]
ICLK[1:28]/ISIG[1:28]
IFP[1:28]
RxCLK[1:28]
RxD[1:28]
RJAT
Frame
Digital Jitter
Attenuator
ISIF
Ingress
Interface
Alignment,
Alarm
Extraction
RECEIVER
T1/E1 Diagnostic Digital Loopback
When Diagnostic Digital loopback is initiated, by writing a 1 to the DLOOP bit in
the T1/E1 Diagnostics register (000DH + N*80H, N=1 to 28), the appropriate
T1/E1 framer in the TEMUX is configured to internally connect its transmit clock
and data (shown as TxD[x] and TxCLK[x] in the diagnostic loopback figure) to the
receive clock and data (shown as RxD[x] and RxCLK[x] in the diagnostic
loopback figure) The data flow through a single T1/E1 framer in this loopback
condition is illustrated in Figure 40.
PROPRIETARY AND CONFIDENTIAL
205
PMC [ PMC-SIERRA, INC ]
