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PM8315-PI 参数 Datasheet PDF下载

PM8315-PI图片预览
型号: PM8315-PI
PDF下载: 下载PDF文件 查看货源
内容描述: 具有集成VT / TU映射器和M13多路复用器高密度T1 / E1成帧器 [HIGH DENSITY T1/E1 FRAMER WITH INTEGRATED VT/TU MAPPER AND M13 MULTIPLEXER]
分类和应用: 复用器数字传输控制器电信电路异步传输模式ATM
文件页数/大小: 329 页 / 2898 K
品牌: PMC [ PMC-SIERRA, INC ]
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STANDARD PRODUCT  
PM8315 TEMUX  
DATASHEET  
PMC-1981125  
ISSUE 7  
HIGH DENSITY T1/E1 FRAMER WITH  
INTEGRATED VT/TU MAPPER AND M13 MUX  
octet unused. Both these rate adjustments are indicated by the SBI control  
signals.  
Transparent VTs (TVTs) can float in the SBI structure in two ways. The first  
method uses valid V1 and V2 pointers to indicate positive and negative pointer  
justifications. The second methods uses the SBI signals SDV5, SAV5, SDPL and  
SAPL to indicate rate adjustments. In the DROP bus the TEMUX will always  
provide both valid pointers with valid SDV5 and SDPL signals. On the SBI Add  
Bus the TEMUX needs to be configured on a per tributary basis for either  
transparent VT mode. Transparent VT operation is configured on a per tributary  
basis via the ETVT and ETVTPTRDIS bits in the TTMP Tributary control  
registers. Note that the SC1FPEN bit in Register 1209H (SONET/SDH Master  
DS3 Clock Generation Control) must be set appropriately for TVT mode.  
On the DROP BUS the TEMUX is timing master as determined by the arrival rate  
of data over the SBI.  
On the ADD BUS the TEMUX can be either the timing master or the timing slave.  
When the TEMUX is the timing slave it receives its transmit timing information  
from the arrival rate of data across the SBI ADD bus. When the TEMUX is the  
timing master it signals devices on the SBI ADD bus to speed up or slow down  
with the justification request signal, SAJUST_REQ. The TEMUX as timing  
master indicates a speedup request to a Link Layer SBI device by asserting the  
justification request signal high during the V3 or H3 octet. When this is detected  
by the Link Layer it will speed up the channel by inserting extra data in the next  
V3 or H3 octet. The TEMUX indicates a slowdown request to the Link Layer by  
asserting the justification request signal high during the octet after the V3 or H3  
octet. When detected by the Link Layer it will retard the channel by leaving the  
octet following the next V3 or H3 octet unused. Both advance and retard rate  
adjustments take place in the frame or multi-frame following the justification  
request.  
SBI Link Rate Information  
The TEMUX SBI bus provides a method for carrying link rate information  
between devices. This is optional on a per channel basis. Two methods are  
specified, one for T1 and E1 channels and the second for DS3 channels. Link  
rate information is not available for TVTs. These methods use the reference  
19.44MHz SBI clock and the SC1FP frame synchronization signal to measure  
channel clock ticks and clock phase for transport across the bus.  
The T1 and E1 method allows for a count of the number of T1 or E1 rising clock  
edges between 2 KHz SC1FP frame pulses. This count is encoded in  
ClkRate[1:0] to indicate that the nominal number of clocks, one more than  
nominal or one less than nominal should be generated during the SC1FP period.  
PROPRIETARY AND CONFIDENTIAL  
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