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PM8316 参数 Datasheet PDF下载

PM8316图片预览
型号: PM8316
PDF下载: 下载PDF文件 查看货源
内容描述: 高密度84通道T1 / E1 / J1成帧器,集成VT / TU映射器和M13 [High Density 84-Channel T1/E1/J1 Framer with Integrated VT/TU Mappers and M13]
分类和应用:
文件页数/大小: 2 页 / 42 K
品牌: PMC [ PMC-SIERRA, INC ]
 浏览型号PM8316的Datasheet PDF文件第2页  
Preliminary
PM8316
TEMUX-84
High Density 84-Channel T1/E1/J1 Framer with Integrated VT/TU Mappers and M13
FEATURES
The PM8316 TEMUX-84 is a 155 Mbit/s
multi-channel T1/E1 Framer with
integrated VT/TU Mappers and M13
Multiplexers.
• This monolithic device integrates:
84 T1 framers
63 E1 framers
Three SONET/SDH
VT1.5/VT2/TU11/TU12 bit
asynchronous or byte synchronous
mappers
Three full featured M13 multiplexers
with DS3 framers
Three SONET/SDH DS3 mappers
for terminating DS3 multiplexed T1
streams, SONET/SDH mapped T1
streams or SONET/SDH mapped
E1 streams
• Each SPE/STS-1 can be
independently programmed for various
T1, E1 or DS3 modes of operation.
• Supports wide range of T1, E1 and J1
framing formats.
• Supports M23 and C-bit parity DS3
formats.
• Stand-alone unchannelized E3 framer
mode (ITU-T Rec. G.751 or G.832) for
access to the entire E3 payload.
• Flexible line side and system side
interface support :
Provides a 19.44 or 77.76 MHz
SONET/SDH Add/Drop Telecom
bus interface for seamless
connection with PMC’s
SONET/SDH devices.
Supports a byte serial Scaleable
Bandwidth Interconnect (SBI™) bus
interface at either 19.44 MHz or
77.76 MHz for high density system
side device interconnection to
PMC’s link layer products.
Supports 8 Mbit/s H-MVIP on the
system interface for all T1 or E1
links, a separate 8 Mbit/s H-MVIP
system interface for all T1 or E1
CAS channels and a separate
8 Mbit/s H-MVIP system interface
for all T1 or E1 CCS and V5.1/V5.2
channels.
Support for transparent virtual
tributaries when SBI interface is
used with SONET/SDH mapper.
Supports insertion and extraction of
arbitrary rate (eg. fractional DS3)
data streams to/from the SBI bus
interface.
• Provides jitter attenuation in the T1/E1
tributary receive and transmit
directions.
• Provides three independent de-jittered
T1 or E1 recovered clocks for system
timing and redundancy.
• Provides per link diagnostic and line
loopbacks.
• Provides PRBS generators and
detectors at DS3 and E3 rates and on
each tributary for error testing at T1,
E1 and NxDS0 rates as recommended
in ITU-T O.151, 0.152.
• Feature-rich functional software drivers
available with device.
• Provides a generic 8-bit
microprocessor bus interface for
configuration, control and status
monitoring.
• Provides a standard 5 signal P1149.1
JTAG test port for boundary scan
board test purposes.
VOLTAGE
• Low power 1.8 V/3.3 V CMOS
technology. All pins are 5 V tolerant.
PACKAGE
• 324-pin fine pitch PBGA package
(23 mm x 23 mm).
• Supports industrial temperature range
(-40
o
C to 85
o
C) operation.
BLOCK DIAGRAM
Telecom
Bus
19.44/77.76 MHz
Mapper
and
Telecom
Bus I/F
M13
M13
Multiplex
Multiplex
er
M13 Mux
er
DS3
DS3
Framer
Framer
DS3/E3
with
with
Framer
PRBS
PRBS
with
PRBS
T1/E1
Framer
RJAT
84xT1/63xE1
on 21 H-MVIP buses
PRBS
Scaleable Bandwidth
Interconnect Bus
19.44/77.76 MHz
PMON
T1/E1
Transmitter
3xDS3
TJAT
DS3
Clock and Data
PMC-2001514 (p2)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2001