PM8399 SXP 24x3GSec
24-Port SAS Expander with Secure Zoning
Released
Product Brief
PRODUCT OVERVIEW
The PM8399 SXP 24x3GSec device is a 24-port SAS expander with
secure zoning capabilities.
•
Integrated MIPS-Powered processor for SAS SMP functions and SES
support.
•
Three configurable multi-master or slave mode TWI interfaces for
device configuration and control of external interfaces.
•
UART interface for system monitoring and debugging support.
•
SFF-8485 compliant SGPIO interface provides expansion for up to
PRODUCT HIGHLIGHTS
•
Secure zoning capabilities as specified in T10 05-144 SAS-2 Zoning.
•
STP initiator capability.
•
Supports IPMB over TWI.
•
Pin- and firmware-compatible with the PM8388 SXP 24x3G device.
•
Virtual SSP support.
•
Low-latency connection arbitration
•
Supports standard and zone-aware table routing of 1024 entries,
144 GPIOs.
ZONING FEATURES
•
Supports 128 groups or domains.
•
SMP for PHY group assignment.
•
Supports zoning fabric supervisor privileges.
•
Transparent to SAS Initiators and Targets.
•
Compatible with legacy SAS Expanders.
direct routing and subtractive routing.
•
Integrated non-blocking cross bar switch allows any-port to any-
HIGH-SPEED I/O
•
1.5 Gbit/s and 3.0 Gbit/s operation.
•
Automatic negotiation of link speed.
•
Accepts Spread Spectrum Clocking (SSC) from SATA HDDs.
•
Programmable transmit pre-emphasis and receiver equalization.
•
Programmable transmit output swing to support both SATA and SAS
port connections.
•
Arbitrary SAS wide-port configurations.
•
STP bridge function allows for either SAS or SATA target devices to be
attached to any port.
levels.
BLOCK DIAGRAM
CSU
REQ/
REQ_SND
•
Integrated resistive termination and AC coupling.
Arbiter
ECM
BPP
PM8399
SXP 24x3GSec
STATISTICS AND PERFORMANCE MONITORING
•
Per-port error counters to provide comprehensive diagnostic
rx0 +/-
tx0 +/-
rx1 +/-
tx1 +/-
rx2 +/-
tx2 +/-
SERDES
PHY
SXL
functions.
•
Programmable performance monitoring counters and interrupt
SERDES
PHY
SXL
SERDES
PHY
SXL
generation.
MUX
datapath
(ECR)
...
...
...
SERDES
PHY
SXL
SERDES
PHY
SXL
•
Per-link PRBS and CJPAT pattern generator for link-integrity
Multi-
Master
Two Wire
I/F (3)
TWI Clock
TWI Data
TWI Reset
UART Data Out
diagnostics.
rx22 +/-
tx22 +/-
rx23 +/-
tx23 +/-
25x25
XBAR
PHYSICAL
•
0.13
μm
(3.3 V I/O supply and 1.2 V core) CMOS technology.
•
27 x 27 mm 352-pin CSBGA package.
UART
PACK
SES
Address Bus
Data Bus
Write Enable
Output Enable
Chip Enable
Local
Bus
I/F
32-bit MIPS
core
SMP
32K
Cache
128K
Scratch
RAM
Bridge
Interrupt
Controller
EJTAG
Debug Port
UART Data In
Request to Send
Clear to Send
SGPIO Clock
SGPIO
SGPIO Load
SGPIO Data Out
SGPIO Data In
Timers
Reference Clock
System Reset
Interrupt
PMC-2050741, Issue 2
© Copyright PMC-Sierra, Inc. 2006
All rights reserved. Proprietary and Confidential to PMC-Sierra, Inc. and for its customers’ internal use.
TDBG
TDO
TDI
TMS
TCK
TRSTB
PMC [ PMC-SIERRA, INC ]
