Released
PMC-Sierra, Inc.
PM9311/2/3/5 ETT1™ CHIP SET
Data Sheet
PMC-2000164
ISSUE 3
ENHANCED TT1™ SWITCH FABRIC
3.1 EPP DATA FLOWS AND BLOCKS
This section describes the functionality of the EPP and its basic structure.
Figure 59. Functional Diagram of LCS Enhanced Port Processor
Input EPP
Output EPP
Control to iDS
p2d_d[6:0]_ic
Grant/Data to iDS Request/Data from iDS
p2d_d[2:0]_id d2p_d[2:0]_id
Control to oDS Data from oDS
p2d_d[6:0]_oc d2p_d[1:0]_od
LCS Grant
Manager
Output
Queue
Manager
Input
Queue
Manager
Output
Scheduler
Grant
Matching
oTIB
TDM
Frame
Tables
iTIB
Scheduler
Request
Modulator
Grant from Scheduler
s2p_s[1:0]
Request to Scheduler
p2s_s[1:0]
MC Backpressure to Scheduler
p2s_s[1:0]
Routing Tag from Scheduler
s2p_s[1:0]
UC Backpressure from FlowControl Crossbars
f2p_[ab][1:0]
UC Backpressure to FlowControl Crossbars
p2f_[ab][1:0]
core clocks
OOB Interface
JTAG
Control/Status Registers
ref_clk(n)
plllock
PLL
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
153
PMC [ PMC-SIERRA, INC ]
