RM7000C
Preliminary
64-Bit MIPS RISC Microprocessor with Integrated L2 Cache
FEATURES
• Dual-Issue symmetric superscalar
microprocessor
•
600MHz max CPU frequency
•
Capable of issuing two instructions
per clock cycle
• Integrated primary and secondary
caches
•
16KB Instruction, 16KB Data, and
256KB on-chip secondary
•
All are 4-way set associative with
32-byte line size
•
Per-line locking in primary and
secondary caches
•
Fast Packet Cache™ increases
system efficiency in networking
applications
• Integrated external cache controller
•
Allows up to 64Mbyte of external
cache for applications with large
data sets
•
Enhanced protocol eliminates
requirement for TAG RAMS
• High-performance system interface
1600 Mbyte per-second peak
throughput
•
200 MHz max. freq., HSTL
multiplexed address/data bus
(SysAD200)
•
Supports two outstanding reads with
out-of-order return
High-performance floating-point unit
•
1200 MFLOPS maximum
•
IEEE754 compliant single and
double precision floating-point
operations
64-bit MIPS instruction set architecture
•
Data PREFETCH instruction allows
the processor to overlap cache miss
latency and instruction execution
•
Single-cycle floating-point multiply-
add
Integrated memory management unit
•
Fully associative TLB
•
64/48 dual entries map 128/96
pages
•
Variable page size
Embedded application enhancements
•
•
•
•
•
•
Fourteen fully prioritized vectored
interrupts-10 external, 2 internal, 2
software
Specialized DSP integer Multiply-
Accumulate instructions
(MAD/MADU), and three-operand
Multiply instruction (MUL)
I and D Test/Break-point (Watch)
registers for emulation and debug
Performance counter for system
and software tuning and debug
•
PACKAGING
•
•
Fully Static 0.13µ CMOS design
with dynamic power down logic
304 pin TBGA package, 31x31 mm
•
DEVELOPMENT TOOLS
• Operating Systems:
•
Linux by MontaVista and Red Hat
•
VxWorks by Wind River Systems
•
Nucleus by Accelerated Technology
•
Neutrino by QNX Software Systems
• Compiler Suites
•
BLOCK DIAGRAM
64-bit Integer Unit
Dual-Issue Superscalar
Integer Multiplier
System Control
PC Unit
64-bit FP Unit
Double/Single IEEE754
Instr. Dispatch
I-Cache
16KB, 4-way, lockable
MMU
Fully Assoc., 48 or 64 Entry
D-Cache
16KB, 4-way, lockable
Bus Interface Unit
L3 Cache Control
System Cache (L2)
Int Ctlr
256KB, 4-way, lockable
SysA /D Bus & L3 Ctr
NMI, INT9 – INT0
PMC- 2011604(P1)
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
© Copyright PMC-Sierra, Inc. 2000
PMC [ PMC-SIERRA, INC ]
