TISP7070H3SL THRU TISP7095H3SL, TISP7125H3SL THRU TISP7210H3SL
TISP7250H3SL THRU TISP7400H3SL
TRIPLE BIDIRECTIONAL THYRISTOR OVERVOLTAGE PROTECTORS
MARCH 1999 - REVISED MARCH 2000
If the impulse generator current exceeds the protectors current rating then a series resistance can be used to
reduce the current to the protectors rated value and so prevent possible failure. The required value of series
resistance for a given waveform is given by the following calculations. First, the minimum total circuit
impedance is found by dividing the impulse generators peak voltage by the protectors rated current. The
impulse generators fictive impedance (generators peak voltage divided by peak short circuit current) is then
subtracted from the minimum total circuit impedance to give the required value of series resistance. In some
cases the equipment will require verification over a temperature range. By using the rated waveform values
from Figure 10, the appropriate series resistor value can be calculated for ambient temperatures in the range
of -40 °C to 85 °C.
a.c. power testing
The protector can withstand the G return currents applied for times not exceeding those shown in Figure 8.
Currents that exceed these times must be terminated or reduced to avoid protector failure. Fuses, PTC
(Positive Temperature Coefficient) resistors and fusible resistors are overcurrent protection devices which can
be used to reduce the current flow. Protective fuses may range from a few hundred milliamperes to one
ampere. In some cases it may be necessary to add some extra series resistance to prevent the fuse opening
during impulse testing. The current versus time characteristic of the overcurrent protector must be below the
line shown in Figure 8. In some cases there may be a further time limit imposed by the test standard (e.g. UL
1459 wiring simulator failure).
capacitance
The protector characteristic off-state capacitance values are given for d.c. bias voltage, V
D
, values of 0, -1 V,
-2 V and -50 V. Where possible values are also given for -100 V. Values for other voltages may be calculated
by multiplying the V
D
= 0 capacitance value by the factor given in Figure 6. Up to 10 MHz the capacitance is
essentially independent of frequency. Above 10 MHz the effective capacitance is strongly dependent on
connection inductance. For example, a printed wiring (PW) trace of 10 cm could create a circuit resonance
with the device capacitance in the region of 50 MHz. In many applications, the typical conductor bias voltages
will be about -2 V and -50 V. Figure 7 shows the differential (line unbalance) capacitance caused by biasing
one protector at -2 V and the other at -50 V.
normal system voltage levels
The protector should not clip or limit the voltages that occur in normal system operation. For unusual
conditions, such as ringing without the line connected, some degree of clipping is permissible. Under this
condition, about 10 V of clipping is normally possible without activating the ring trip circuit.
DRM
value at temperatures below 25 °C. The calculated value
should not be less than the maximum normal system voltages. The TISP3290H3, with a V
DRM
of 220 V, can
be used for the protection of ring generators producing 105 V rms of ring on a battery voltage of -58 V. The
peak ring voltage will be 58 + 1.414*105 = 206.5 V. However, this is the open circuit voltage and the
connection of the line and its equipment will reduce the peak voltage.
For the extreme case of an unconnected line, the temperature at which clipping begins can be calculated
using the data from Figure 9. To possibly clip, the V
DRM
value has to be 206.5 V. This is a reduction of the
220 V 25 °C V
DRM
value by a factor of 206.5/220 = 0.94. Figure 9 shows that a 0.94 reduction will occur at an
ambient temperature of -32 °C. In this example, the TISP3290H3 will allow normal equipment operation, even
on an open-circuit line, provided that the minimum expected ambient temperature does not fall below -32 °C.
JESD51 thermal measurement method
To standardise thermal measurements, the EIA (Electronic Industries Alliance) has created the JESD51
standard. Part 2 of the standard (JESD51-2, 1995) describes the test environment. This is a 0.0283 m
3
(1 ft
3
)
cube which contains the test PCB (Printed Circuit Board) horizontally mounted at the centre. Part 3 of the
PRODUCT
INFORMATION
10
POINN [ POWER INNOVATIONS LTD ]
