PO100HSTL50A
Dual Differential LVDS/LVPECL/HSTL to LVTTL Translator
Dual LVTTL/LVCMOS to Differential HSTL Translator
FEATURES:
•
Patented Technology
•
Differential LVDS/LVPECL/HSTL to LVTTL
Translator
- Operating frequency up to 1GHz with 2pf load
- Operating frequency up to 800MHz with 5pf load
- Operating frequency up to 450MHz with 15pf load
- Very low output pin to pin skew < 150ps
- Propagation delay < 1.8ns max with 15pf load
•
LVTTL/LVCMOS to Differential HSTL Translator
- Operating frequency up to 1.65GHz with 5pf load
- Operating frequency up to 500MHz with 15pf load
- Very low output pin to pin skew < 100ps
- Propagation delay < 1.4ns max with 15pf load
•
2.4V to 3.6V power supply
•
Industrial temperature range: –40°C to 85°C
•
Available in 16-pin 150ml SOIC package
04/19/09
DESCRIPTION:
Potato Semiconductor’s PO100HSTL50A is
designed for world top performance using
submicron CMOS technology to achieve 1GHz
LVTTL output frequency with less than 1.8ns
propagation delay and 1.65GHz HSTL output
frequency with less than 1.4ns propagation delay.
The
PO100HSTL50A
is a low-skew, The small
outline 16 pin package and the low skew design to
make it ideal for applications which require the
translation of a clock or a data signal.
Pin Configuration
1B
1A
1R
RE
2R
2A
2B
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Logic Block Diagram
V
CC
1D
1Y
1Z
DE
2Z
2Y
2D
1D
DE
2D
15
12
9
14
13
10
11
2
1
6
7
1Y
1Z
2Y
2Z
1A
1B
2A
2B
1R
RE
2R
3
4
5
Pin Description
RECEIVER INPUTS
V
ID
= V
A
– V
B
V
ID
≥
50 mV
50 MV < V
ID
< 50 mV
V
ID
≤
–50 mV
Open
X
RE
L
L
L
L
H
RECEIVER OUTPUT
R
H
?
L
H
Z
DRIVER INPUTS
D
L
H
Open
X
DE
H
H
H
L
DRIVER OUTPUTS
Y
L
H
L
Z
Z
H
L
H
Z
1
Copyright
© Potato Semiconductor Corporation
POTATO [ POTATO SEMICONDUCTOR CORPORATION ]
