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PO100HSTL180ASR 参数 Datasheet PDF下载

PO100HSTL180ASR图片预览
型号: PO100HSTL180ASR
PDF下载: 下载PDF文件 查看货源
内容描述: 差分LVDS / LVPECL / HSTL到LVTTL翻译LVTTL / LVCMOS到差分HSTL翻译 [Differential LVDS/LVPECL/HSTL to LVTTL Translator LVTTL/LVCMOS to Differential HSTL Translator]
分类和应用:
文件页数/大小: 8 页 / 688 K
品牌: POTATO [ POTATO SEMICONDUCTOR CORPORATION ]
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PO100HSTL180A
Differential LVDS/LVPECL/HSTL to LVTTL Translator
LVTTL/LVCMOS to Differential HSTL Translator
FEATURES:
Patented Technology
Differential LVDS/LVPECL/HSTL to LVTTL
Translator
- Operating frequency up to 1GHz with 2pf load
- Operating frequency up to 800MHz with 5pf load
- Operating frequency up to 450MHz with 15pf load
- Very low output pin to pin skew < 150ps
- Propagation delay < 1.8ns max with 15pf load
LVTTL/LVCMOS to Differential HSTL Translator
- Operating frequency up to 1.65GHz with 5pf load
- Operating frequency up to 500MHz with 15pf load
- Very low output pin to pin skew < 100ps
- Propagation delay < 1.4ns max with 15pf load
2.4V to 3.6V power supply
Industrial temperature range: –40°C to 85°C
Available in 14-pin 150ml SOIC package
04/26/09
DESCRIPTION:
Potato Semiconductor’s PO100HSTL180A is
designed for world top performance using
submicron CMOS technology to achieve 1GHz
LVTTL output frequency with less than 1.8ns
propagation delay and 1.65GHz HSTL output
frequency with less than 1.4ns propagation delay.
The
PO100HSTL180A
is a low-skew, The small
outline 14 pin package and the low skew design to
make it ideal for applications which require the
translation of a clock or a data signal.
Pin Configuration
NC
R
RE
DE
D
GND
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
Logic Block Diagram
V
CC
V
CC
A
B
Z
Y
NC
D
DE
RE
R
5
4
3
2
9
10
Y
Z
12
11
A
B
Pin Description
RECEIVER INPUTS
V
ID
= V
A
– V
B
V
ID
10 mV
10 mV < V
ID
< 10 mV
V
ID
–10 mV
Open
X
RE
L
L
L
L
H
RECEIVER OUTPUT
R
H
?
L
H
Z
DRIVER INPUTS
D
L
H
Open
X
DE
H
H
H
L
DRIVER OUTPUTS
Y
L
H
L
Z
Z
H
L
H
Z
1
Copyright
© Potato Semiconductor Corporation