DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
PO54G74A, PO74G74A
10/10/07
54, 74 Series GHz Logic
FEATURES:
. Patented technology
. Specified From –40°C to 85°C, –40°C to 125°C,
and –55°C to 125°C
. Operating frequency is faster than 600MHz
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 2ns max with 15pf load
. Low input capacitance: 4pf typical
. Latch-Up Performance Exceeds 250 mA Per
JESD 17
. ESD Protection Exceeds JESD 22
. 5000-VHuman-BodyModel (A114-A)
. 200-VMachineModel (A115-A)
. Available in 14pin 150mil wide SOIC package
. Available in 14pin Ceramic Dual Flatpack
. Available in 20pin Leadless Ceramic Chip Carrier
DESCRIPTION:
Potato Semiconductor’s PO74G74A is designed for
world top performance using submicron CMOS
technology to achieve higher than 600MHz TTL
/CMOS output frequency with less than 2ns propaga-
tion delay.
This dual D flip-flop is designed for 1.65-V to 3.6-V
V
CC
operation.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
1CLR
NC
V
CC
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
1CLK
NC
1PRE
NC
1Q
4
5
6
7
3
2 1 20 19
18
17
16
2CLR
2D
NC
2CLK
NC
2PRE
14
Vcc
2CLR
2D
2CLK
2PRE
2Q
2Q
13
12
11
10
9
8
15
14
8
9 10 11 12 13
1Q
GND
NC
Q
L
H
H
L
H
Q
0
1PRE
1Q
1Q
GND
4
5
6
CLR
7
D
PRE
1D
1CLR
1CLR
1
2
3
D
PRE
1D
Pin Description
INPUTS
PRE
L
H
L
H
H
H
CLR
H
L
L
H
H
H
CLK
X
X
X
↑
↑
L
D
X
X
X
H
L
X
OUTPUTS
Q
H
L
H
H
L
Q
0
Logic Block Diagram
1
CLR
2
2Q
2Q
Q
Q
Q
Q
1
Copyright
© Potato Semiconductor Corporation
POTATO [ POTATO SEMICONDUCTOR CORPORATION ]
