PO54G00A, PO74G00A
QUADRUPLE 2-INPUT POSITIVE-NAND GATE
54, 74 Series GHz Logic
FEATURES:
. Patented technology
. Specified From –40°C to 85°C, –40°C to 125°C,
and –55°C to 125°C
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 750MHz with 5pf load
. Operating frequency up to 350MHz with 15pf load
. V
CC
Operates from 1.65V to 3.6V
. Propagation delay < 1.5ns max with 15pf load
. Low input capacitance: 4pf typical
. Latch-Up Performance Exceeds 250 mA Per
JESD 17
. ESD Protection Exceeds JESD 22
. 5000-VHuman-BodyModel (A114-A)
. 200-VMachineModel (A115-A)
. Available in 14pin 150mil wide SOIC package
. Available in 14pin Ceramic Dual Flatpack
. Available in 20pin Leadless Ceramic Chip Carrier
01/12/09
DESCRIPTION:
Potato Semiconductor’s PO74G00A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL/CMOS output
frequency with less than 1.5ns propagation delay.
This quadruple 2-input positive-NAND gate is
designed for 1.65-V to 3.6-V V
CC
operation.
The PO74G00A performs the Boolean function
Y= A
·
B or Y= A + B in positive logic.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
1A
1B
1Y
2A
2B
2Y
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V CC
4B
4A
4Y
3B
3A
3Y
1Y
NC
2A
NC
2B
1B
1A
NC
V
CC
4B
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
4A
NC
4Y
NC
3B
Pin Description
INPUTS
A
H
L
X
B
H
X
L
OUTPUT
Y
L
H
H
Logic Block Diagram
A
B
Y
1
Copyright
© 2005-2007, Potato Semiconductor Corporation
2Y
GND
NC
3Y
3A
POTATO [ POTATO SEMICONDUCTOR CORPORATION ]
