DUAL NEGATIVE-EDGE-TRIGGERED J-K FLIP-FLOP
WITH CLEAR AND PRESET
PO74G112A
04/19/09
74 Series GHz Logic
FEATURES:
. Patented technology
. Specified From –40°C to 85°C, –40°C to 125°C,
and –55°C to 125°C
. Operating frequency up to 750MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 2ns max with 15pf load
. Low input capacitance: 4pf typical
. Latch-Up Performance Exceeds 250 mA Per
JESD 17
. ESD Protection Exceeds JESD 22
. 5000-VHuman-BodyModel (A114-A)
. 200-VMachineModel (A115-A)
. Available in 16pin 150mil wide SOIC package
. Available in 16pin 173mil wide TSSOP package
DESCRIPTION:
Potato Semiconductor’s PO74G112A is designed for
world top performance using submicron CMOS
technology to achieve 750MHz TTL /CMOS output
frequency with less than 2ns propagation delay.
This dual negative-edge-triggered J-K flip-flop is
designed for 1.65-V to 3.6-V V
CC
operation.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
1CLK
1K
1J
1PRE
1Q
1Q
2Q
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Logic Block Diagram
V
CC
1CLR
2CLR
2CLK
2K
2J
2PRE
2Q
Pin Description
INPUTS
PRE
L
H
L
H
H
H
H
H
CLR
H
L
L
H
H
H
H
H
CLK
X
X
X
↓
↓
↓
↓
H
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
Q
0
OUTPUTS
Q
H
L
H
Q
0
H
L
Toggle
Q
0
Q
L
H
H
Q
0
L
H
1CLK
1K
1J
1PRE
1Q
1Q
2Q
GND
J
K
PRE
Q
1
Q
CLR
J
K
PRE
Q
1
Q
CLR
V
CC
1CLR
2CLR
2CLK
2K
2J
2PRE
2Q
1
Copyright
© Potato Semiconductor Corporation
POTATO [ POTATO SEMICONDUCTOR CORPORATION ]
