欢迎访问ic37.com |
会员登录 免费注册
发布采购

PO74G126ASR 参数 Datasheet PDF下载

PO74G126ASR图片预览
型号: PO74G126ASR
PDF下载: 下载PDF文件 查看货源
内容描述: 四路总线缓冲器闸具有三态输出 [QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS]
分类和应用: 输出元件
文件页数/大小: 6 页 / 496 K
品牌: POTATO [ POTATO SEMICONDUCTOR CORPORATION ]
 浏览型号PO74G126ASR的Datasheet PDF文件第2页浏览型号PO74G126ASR的Datasheet PDF文件第3页浏览型号PO74G126ASR的Datasheet PDF文件第4页浏览型号PO74G126ASR的Datasheet PDF文件第5页浏览型号PO74G126ASR的Datasheet PDF文件第6页  
QUADRUPLE BUS BUFFER GATE
WITH 3-STATE OUTPUTS
PO74G126A
02/07/07
74 Series GHz Logic
FEATURES:
. Patented technology
. Operating frequency up to 1.125GHz with 2pf load
. Operating frequency up to 700MHz with 5pf load
. Operating frequency up to 400MHz with 15pf load
. VCC Operates from 1.65V to 3.6V
. Propagation delay < 1.5ns max with 15pf load
. Low input capacitance: 4pf typical
. Available in 14pin 150mil wide SOIC package
DESCRIPTION:
Potato Semiconductor’s PO74G126A is designed for
world top performance using submicron CMOS
technology to achieve 1.125GHz TTL /CMOS output
frequency with less than 1.5ns propagation delay.
This quadruple bus buffer gate is designed for 1.65-V
to 3.6-V V
CC
operation.
The
PO74G126A
featuresindependent
linedriverswith3-stateoutputs. Eachoutput isdisabled-
whenthe associatedoutput-enable(OE)input islow.
Inputs can be driven from either 3.3V or 5V devices.
This feature allows the use of these devices as
translators in a mixed 3.3V/5V system environment.
Pin Configuration
1OE
1A
1Y
2OE
2A
2Y
GND
Logic Block Diagram
V
CC
4OE
4A
4Y
2OE
4
5
6
1OE
1A
1
2
3
1
2
3
4
5
6
7
14
13
12
11
10
9
8
1Y
3OE
3A
3Y
3OE
10
9
8
2A
2Y
Pin Description
INPUTS
OE
H
H
L
A
H
L
X
OUTPUT
Y
H
L
Z
3A
3Y
4OE
4A
13
12
11
4Y
1
Copyright
© Potato Semiconductor Corporation