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PO74HSTL85331A 参数 Datasheet PDF下载

PO74HSTL85331A图片预览
型号: PO74HSTL85331A
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V 1 : 4的晶体振荡器/差分时钟或数据扇出缓冲器 [3.3V 1:4 Crystal Oscillator/ Differential Clock or Data Fanout Buffer]
分类和应用: 振荡器晶体振荡器时钟
文件页数/大小: 8 页 / 670 K
品牌: POTATO [ POTATO SEMICONDUCTOR CORPORATION ]
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3.3V 1:4 Crystal Oscillator/
Differential Clock or Data Fanout Buffer
PO74HSTL85331A
03/01/07
700MHz HSTL Potato Chip
FEATURES:
. Patented Technology
. Four HSTL differential outputs
. Selectable differential CLK, nCLK or crystal inputs
. CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
. Operating frequency up to 700MHz with 2pf load
. Operating frequency up to 550MHz with 5pf load
. Operating frequency up to 400MHz with 15pf load
. Very low output pin to pin skew < 50ps
. 3.3-ns propagation delay (typical)
. 2.4V to 3.6V power supply
. Industrial temperature range: –40°C to 85°C
. 20-pin TSSOP package
DESCRIPTION:
The PO74HSTL85331A is a low skew, high performance
1-to-4 Crystal Oscillator/Differential-to-3.3V HSTL
fanout buffer of High Performance Clock Solutions from
PotatoSemi. The PO74HSTL85331A has selectable
differential clock or crystal inputs. The CLK, nCLK pair
can accept most standard differential input levels. The
clock enable is internally synchronized to eliminate runt
pulses on the outputs during asynchronous
assertion/deassertion of the clock enable pin.
Guaranteed output and part-to-part skew characteristics
make the PO74HSTL85331A ideal for those applications
demanding well defined performance and repeatability.
Pin Configuration
V
EE
CLK_EN
CLK_SEL
CLK
nCLK
XTAL1
XTAL2
nc
nc
V
CC
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
Q0
nQ0
V
CC
Q1
nQ1
Q2
nQ2
V
CC
Q3
nQ3
Logic Block Diagram
CLK_EN
D
Q
LE
CLK
nCLK
XTAL1
XTAL2
CLK_SEL
0
1
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
1
Copyright
© Potato Semiconductor Corporation