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LP3205-33B5F 参数 Datasheet PDF下载

LP3205-33B5F图片预览
型号: LP3205-33B5F
PDF下载: 下载PDF文件 查看货源
内容描述: 1.5MHZ , 800毫安,高效率同步PWM降压型DC / DC转换 [1.5MHZ,800mA,High Efficiency Synchronous PWM Step-Down DC/DC Convert]
分类和应用:
文件页数/大小: 10 页 / 354 K
品牌: POWER [ LOWPOWER SEMICONDUCTOR INC ]
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Preliminary Datasheet
Efficiency= 100%- (L1+L2+L3…)
Where L1、L2, etc. are the individual losses as a percentage of
Input power .although all dissipative elements in the for most
of losses: VIN quiescent current and 1
2
R loss dominates the
efficiency loss at medium to high load currents. In a typical
efficiency plot, the efficiency curve at very low load currents
can be misleading since the actual power lost is of no
consequence.
LP3205
2. 1
2
Rlosses tae calculated from the resistances of the internal
switches, R
SW
and external inductor R
L
. in continuous mode
the average output current flowing through inductor L is
“chopped” between the main switch and the synchronous
switch. Thus, the series resistance looking into the LX pin is a
function of both top and bottom MOSFER R
DS(ON)
and the duty
cycle (DC) as follows:
The R
DS(ON)
for both the top and bottom MOSFETS can be
obtained from the typical performance characteristics curves.
thus, to obtain 1
2
R losses, simply add R
SW
to R
L
and multiply
the square of the average output current.
1.The VIN quiescent current is due to two components:
the DC Bias current as given in the electrical
characteristics and the Internal main switch and
synchronous switch gate charge currents. the gate
charge current results from switching the gate
capacitance of the internal power MOSFET
switches .Each time the gate charge current. results
from switching the gate capacitance of the internal
power MOSFET switches. Each time the gate is
switches from high to low to high again, a packet of
charge
△Q
moves from V
IN
to ground.
The resulting
△Q/△t
is the current out of V
IN
that is typically
larger than the DC bias current. In continuous mode.
L
GATCHG
=f(Q
T
+Q
B
)
Where Q
T
and Q
B
are the gate charges of the internal top and
bottom switches. Both the DC bias and gate charge losses are
proportional to V
IN
and thus their effects will be more
pronounced at higher supply voltages.
Other losses including C
IN
and C
OUT
ESR dissipative
losses and inductor core losses generally account for
less than 2% of the total loss.
LP3205 – Ver. 1.0 Datasheet
Feb.-2007
Page 8 of 10