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LP3982-25J5F 参数 Datasheet PDF下载

LP3982-25J5F图片预览
型号: LP3982-25J5F
PDF下载: 下载PDF文件 查看货源
内容描述: 300毫安,超低噪音,小包装超高速的CMOS LDO稳压器 [300mA,Ultra-low noise, Small Package Ultra-Fast CMOS LDO Regulator]
分类和应用: 稳压器
文件页数/大小: 8 页 / 374 K
品牌: POWER [ LOWPOWER SEMICONDUCTOR INC ]
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Preliminary Datasheet
Applications Information
Like
any low-dropout regulator, the external capacitors
used with the LP3982 must be carefully selected for
regulator stability and performance. Using a capacitor
whose value is > 1µF on the LP3982 input and the
amount of capacitance can be increased without limit.
The input capacitor must be located a distance of not
more than 0.5 inch from the input pin of the IC and
returned to a clean analog ground. Any good quality
ceramic or tantalum can be used for this capacitor. The
capacitor with larger value and lower ESR (equivalent
series
resistance)
provides
better
PSRR
and
line-transient response. The output capacitor must meet
both requirements for minimum amount of capacitance
and ESR in all LDOs application. The LP3982 is designed
specifically to work with low ESR ceramic output
capacitor in space-saving and performance consideration.
Using a ceramic capacitor whose value is at least 1µF
with ESR is > 25mΩ on the LP3982 output ensures
stability. The LP3982 still works well with output capacitor
of other types due to the wide stable ESR range. Figure 1
shows the curves of allowable ESR range as a function of
load current for various output capacitor values. Output
capacitor of larger capacitance can reduce noise and
improve load transient response, stability, and PSRR.
The output capacitor should be located not more than 0.5
inch from the VOUT pin of the LP3982 and returned to a
clean analog ground.
LP3982
Start-up Function Enable Function
The LP3982 features an LDO regulator enable/disable
function. To assure the LDO regulator will switch on, the
EN turn on control level must be greater than 1.2 volts.
The LDO regulator will go into the shutdown mode when
the voltage on the EN pin falls below 0.4 volts. For to
protecting
the
system,
the
LP3982
have
a
quick-discharge function. If the enable function is not
needed in a specific application, it may be tied to VIN to
keep the LDO regulator in a continuously on state.
Bypass Capacitor and Low Noise
Connecting a 22nF between the BP pin and GND pin
significantly reduces noise on the regulator output, it is
critical that the capacitor connection between the BP pin
and GND pin be direct and PCB traces should be as short
as possible. There is a relationship between the bypass
capacitor value and the LDO regulator turn on time. DC
leakage on this pin can affect the LDO regulator output
noise and voltage regulation performance.
Thermal Considerations
Thermal protection limits power dissipation in LP3982.
When the operation junction temperature exceeds 165°C,
the OTP circuit starts the thermal shutdown function turn
the pass element off. The pass element turn on again
after the junction temperature cools by 30°C. For continue
operation, do not exceed absolute maximum operation
junction temperature 125°C.
LP3982 – Ver. 1.0 Datasheet
Dec.-2006
Page 6 of 8