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LNK414LG 参数 Datasheet PDF下载

LNK414LG图片预览
型号: LNK414LG
PDF下载: 下载PDF文件 查看货源
内容描述: 使用LinkSwitch -PH LED驱动器IC系列 [LinkSwitch-PH LED Driver IC Family]
分类和应用: 驱动器
文件页数/大小: 20 页 / 2117 K
品牌: POWERINT [ POWER INTEGRATIONS, INC. ]
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LNK403-409/413-419
BYPASS (BP)
BYPASS
CAPACITOR
SELECT
SOFT-START
TIMER
FAULT
PRESENT
5.9 V
REGULATOR
DRAIN (D)
HYSTERETIC
THERMAL
SHUTDOWN
-
I
LIM
M
I
AUTO-RESTART
COUNTER
5.9 V
5.0 V
VOLTAGE
MONITOR (V)
1V
STOP
LOGIC
JITTER
CLOCK
OSCILLATOR
3-V
T
UV/OV
LINE
SENSE
-
+
BYPASS PIN
UNDERVOLTAGE
Comparator
FB
OFF
DC
MAX
OCP
+
FEEDBACK (FB)
V
BG
I
V
I
FB
FB
OFF
DC
MAX
PFC/CC
CONTROL
M
I
FEEDBACK
SENSE
REFERENCE (R)
6.4 V
REFERENCE
BLOCK
V
BG
Figure 3.
Functional Block Diagram.
Pin Functional Description
DRAIN (D) Pin:
This pin is the power FET drain connection. It also provides
internal operating current for both start-up and steady-state
operation.
SOURCE (S) Pin:
This pin is the power FET source connection. It is also the
ground reference for the BYPASS, FEEDBACK, REFERENCE and
VOLTAGE MONITOR pins.
BYPASS (BP) Pin:
This is the connection point for an external bypass capacitor for
the internally generated 5.9 V supply. This pin also provides
output power selection through choice of the BYPASS pin
capacitor value.
FEEDBACK (FB) Pin:
The FEEDBACK pin is used for output voltage feedback. The
current into the FEEDBACK pin is directly proportional to the
output voltage. The FEEDBACK pin also includes circuitry to
protect against open load and overload output conditions.
REFERENCE (R) Pin:
This pin is connected to an external precision resistor and is
used to configure for dimming (LNK403-409) and non-TRIAC
dimming (LNK413-419) modes of operation.
VOLTAGE MONITOR (V) Pin:
This pin interfaces with an external input line peak detector,
consisting of a rectifier, filter capacitor and resistors. The
applied current is used to control stop logic for line under-
voltage (UV), overvoltage (OV), provide feed-forward to control
the output current and the remote ON/OFF function.
Exposed Pad
(Backside) Internally
Connected to
SOURCE Pin
E Package (eSIP-7C)
(Top View)
7D
5S
4 BP
3 FB
2V
1R
Exposed Pad
(backside) Internally
Connected to
SOURCE Pin (see
eSIP-7C Package
Drawing)
Figure 4.
Pin Configuration.
2
Rev. D 08/11
+
Gate
Driver
SenseFet
LEB
CURRENT LIMIT
COMPARATOR
-
I
LIM
V
SENSE
I
S
PI-5431-102610
SOURCE (S)
L Package (eSIP-7F)
1 3 5
R FB S
7
Lead Bend Outward
2 4
V BP D
from Drawing
(Refer to eSIP-7F Package
Outline Drawing)
PI-5432-082411
www.powerint.com