LNK562-564
Key Application Considerations
Output Power Table
The data sheet maximum output power table (Table 1) represents
the maximum practical continuous output power level that can
be obtained under the following assumed conditions:
1. The minimum DC input voltage is 90 V or higher for 85 VAC
input, or 240 V or higher for 230 VAC input or 115 VAC with
a voltage doubler. The value of the input capacitance should
be large enough to meet these criteria for AC input designs.
2. Secondary output of 6 V with a Schottky rectifier diode.
3. Assumed efficiency of 70%.
4. Voltage only output (no secondary-side constant current
circuit).
5. Discontinuous mode operation (K
P
>
1).
6. A suitably sized core to allow a practical transformer design
(see Table 2).
7. The part is board mounted with SOURCE pins soldered
to a sufficient area of copper to keep the SOURCE pin
temperature at or below 100 °C.
8. Ambient temperature of 50 °C for open frame designs and an
internal enclosure temperature of 60 °C for adapter designs.
LinkSwitch-LP
Device
Core Size
EE13
EE16
EE19
LNK562
1.1 W
1.3 W
1.9 W
LNK563
1.4 W
1.7 W
2.5 W
LNK564
1.7 W
2W
3W
1.
Clampless
designs should only be used for P
O
≤
2.5 W using
a V
OR
of
≤
90 V
2. For designs with P
O
≤
2 W, a two-layer primary must be
used to ensure adequate primary intra-winding capacitance
in the range of 25 pF to 50 pF.
3. For designs with 2
<
P
O
≤
2.5 W, a bias winding must be added
to the transformer using a standard recovery rectifier diode
(1N4003– 1N4007) to act as a clamp. This bias winding may
also be used to externally power the device by connecting
a resistor from the bias winding capacitor to the BYPASS
pin. This inhibits the internal high-voltage current source,
reducing device dissipation and no-load consumption.
4. For designs with P
O
>2.5
W,
Clampless
designs are not practical
and an external RCD or Zener clamp should be used.
5. Ensure that worst-case, high line, peak drain voltage is below
the BV
DSS
specification of the internal MOSFET and ideally
≤
650 V to allow margin for design variation.
V
OR
(Reflected Output Voltage), is the secondary output plus
output diode forward voltage drop that is reflected to the
primary via the turns ratio of the transformer during the diode
conduction time. The V
OR
adds to the DC bus voltage and the
leakage spike to determine the peak drain voltage.
Audible Noise
The cycle skipping mode of operation used in
LinkSwitch-LP
can generate audio frequency components in the transformer.
To limit this audible noise generation, the transformer should
be designed such that the peak core
fl
ux density is below
1500 Gauss (150 mT). Following this guideline and using the
standard transformer production technique of dip varnishing,
practically eliminates audible noise. Vacuum impregnation
of the transformer is not recommended, as it does not provide
any better reduction of audible noise than dip varnishing. And
although vacuum impregnation has the benefit of increased
transformer capacitance (which helps in
Clampless
designs),
it can also upset the mechanical design of the transformer,
especially if shield windings are used. Higher
fl
ux densities are
possible, increasing the power capability of the transformers
above what is shown in Table 2. However careful evaluation of
the audible noise performance should be made using production
transformer samples before approving the design.
Ceramic capacitors that use dielectrics such as Z5U, when used
in clamp circuits, may also generate audio noise. If this is the
case, try replacing them with a capacitor having a different
dielectric or construction, for example a
fi
lm type.
Bias Winding Feedback
To give the best output regulation in bias winding designs, a
slow diode such as the 1N400x series should be used as the
rectifier. This effectively
fi
lters the leakage inductance spike
and reduces the error that this would give when using fast
recovery time diodes. The use of a slow diode is a requirement
in
Clampless
designs.
Table 2. Estimate of Transformer Power Capability vs.
LinkSwitch-LP Device and Core Size at a Flux Density of
1500 Gauss (150 mT).
Below a value of 1, K
P
is the ratio of ripple to peak primary
current. Above a value of 1, K
P
is the ratio of primary MOSFET
OFF time to the secondary diode conduction time. Due to
the
fl
ux density requirements described below, typically a
LinkSwitch-LP
design will be discontinuous, which also has
the benefit of allowing lower-cost fast (vs. ultra-fast) output
diodes and reducing EMI.
Clampless
Designs
Clampless
designs rely solely on the drain node capacitance
to limit the leakage inductance induced peak drain-to-source
voltage. Therefore the maximum AC input line voltage, the
value of V
OR
, the leakage inductance energy, (a function of
leakage inductance and peak primary current), and the primary
winding capacitance determine the peak drain voltage. With no
significant dissipative element present, as is the case with an
external clamp, the longer duration of the leakage inductance
ringing can increase EMI.
The following requirements are recommended for a universal
input or 230 VAC only
Clampless
design:
5
Rev. H 11/08
POWERINT [ POWER INTEGRATIONS, INC. ]
