PLC810PG
PLC810PG PFC Control Block
The PLC810PG PFC is a boost converter which conditions the
average input current to make it (typically) sinusoidal and in phase
with the input voltage. In normal operation the PFC operates in
continuous conduction mode (CCM). Under light load, depending
on the PFC inductor value, the converter may enter a
discontinuous conduction mode (DCM). The PLC810PG PFC
controller does not need to sense the input voltage. The
PLC810PG PFC controller exploits the fact that the input voltage
(V
IN
) is effectively constant over a few adjacent switching cycles,
because the input is changing at 60 Hz while the switching
frequency is 1500 times higher. Using the average input voltage
and output voltage values, the off-time for the boost converter is:
The voltage developed across the PFC current sense resistor
and applied to the ISP pin is compared against an overcurrent
threshold (which has built in hysteresis). This implements a
pulse-by-pulse current limit to protect the PFC MOSFET against
overcurrent.
The ISP pin voltage is also averaged (over several switching
cycles), and used as an input to the PFC multiplier.
The Discrete Variable Gain Amplifier, DVGA/LPF block is
responsible for averaging the ISP pin voltage (over several
switching cycles) and implementing a multiplier as part of the
PFC control loop, under control of the VCOMP signal.
Using the feedback voltage on FBP, PFC and LLC circuit
protection is provided:
•
PFC overvoltage protection:
The feedback voltage on the
FBP pin is compared against an overvoltage threshold (V
OV(H)
).
If the voltage at the FBP pin is greater than V
OV(H)
, the PFC
MOSFET gate signal is turned OFF immediately, and held off
for at least one cycle. When FBP drops below V
OV(H)
, PFC
switching recommences.
•
Minimum boost voltage detection:
The feedback voltage
on FBP is compared against a minimum boost voltage thresh-
old (V
IN(H)
/V
IN(L)
). The PFC is inhibited if the FBP voltage is below
V
IN(L)
. The gate of the PFC MOSFET is driven via GATEP if the
FBP voltage is above V
IN(H)
). This is done to prevent PFC startup
in brownout or during AC failure conditions.
•
Minimum boost voltage for LLC startup:
The feedback
voltage on FBP is compared against an LLC shutdown voltage
threshold (V
SD(H)
)/ V
SD(L)
). This inhibits LLC startup until the PFC
output voltage is close to regulation. The purpose of V
SD(L)
is to
shutdown the LLC when the PFC output voltage is low (~64%
of nominal), which may occur during AC dropout, shutdown, or
overload conditions.
•
PFC open-loop protection:
The FBP pin includes a high-
impedance (5 MW) pull-down resistor to protect against a
floating FBP pin resulting in an open-loop condition.
PLC810 LLC Control Block
The PLC810PG LLC controller supports half-bridge topologies.
The LLC circuit relies on two switches in a half-bridge topology
driving a resonant tank (LLC) and power transformer. The LLC
circuit has two resonant frequencies: the series resonant
frequency and the parallel resonant frequency. Typically, an
LLC converter is designed to operate at a switching frequency
which is slightly higher than the series resonant frequency when
at nominal input voltage. In this operating region, the MOSFET
switching can be performed at zero voltage, reducing the
switching losses. In the normal mode of operation, the LLC
controller will vary its switching frequency around a narrow
range of frequencies to regulate the output voltage.
Feedback and Maximum Frequency Limit
The PLC810PG LLC controller has nominal operating frequency of
100 kHz. For voltage regulation, with input voltage and load
variations, the operating frequency will vary and may exceed
250 kHz. The maximum frequency set by the resistor on FMAX
pin is typically chosen to be two to three times the nominal
operating frequency. The appropriate maximum frequency is set
D
OFF
=
]
1 -
D
g
=
V
IN
V
O
The input current is the same as the inductor current (sensed
current), thus from the previous equation, it can be deduced
that:
V
V
IN
=
D
OFF
#
O
I
SENSE
I
IN
In order to make the input impedance look resistive, the input
current must be proportional to the input voltage:
V
IN
=
R
E
I
N
Thus, D
off
has to be controlled by:
D
OFF
=
c
R
E
m
#
I
SENSE
V
O
If (D
OFF
) changes slowly with the input voltage, the average
current will be in-phase with the input voltage. The PLC810PG
PFC block controls the PFC off-time (D
OFF
= (1–D)).
The output voltage needs to be regulated and R
E
needs to be
adjusted as a function of the load and the input voltage.
The PLC810PG PFC has two inputs:
•
•
The feed-back PFC output voltage is reduced by a resistor
divider and sensed and via the FBP pin.
The instantaneous inductor current, sensed via the ISP pin.
The PFC output voltage is sensed at the FBP pin through an
external resistive divider so that the desired DC boost voltage
(typically 385 V) is reduced to match the internally generated
V
FBPREF
(2.2 V) reference voltage. The FBP input pin and the
V
FBPREF
voltage are inputs to an operational transconductance
amplifier (OTA). The output of the OTA drives the VCOMP pin,
allowing external compensation of the low frequency voltage loop.
The purpose of the phase alignment block is to set the edges of
the PFC MOSFET gate drive signal to avoid the LLC converter
switching edges. This eliminates switching-noise coupling
between LLC and PFC circuits.
The compensation components are connected between
VCOMP and the analog ground pin (GND). The VCOMP pin is
used to apply compensation to the low frequency voltage loop.
6
Rev. F 08/09
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