TNY284-290
Safety Spacing
Y1-
Capacitor
Maximize hatched copper
areas (
) for optimum
heat sinking
Output
Recti er
+
High-Voltage
Input Filter Capacitor
PRI
BIAS
PRI
Output Filter
Capacitor
-
D
S
S
S
TinySwitch-4
BP/M
BIAS
T
r
a
n
s
f
o
r
m
e
r
SEC
TOP VIEW
S
*C
HF
/C
BP
EN/
UV
C
BP
Opto-
coupler
-
DC
+
OUT
*C
HF
is a 0.1
µF
high frequency noise bypass capacitor (the high frequency 0.1
µF
capacitor eliminates need for C
BP
if I
LIMIT
selection requires 0.1
µF).
PI-6651-060612
Figure 17.
Recommended Circuit Board Layout for TinySwitch-4 with Undervoltage Lock Out Resistor.
Y Capacitor
The placement of the Y capacitor should be directly from the
primary input filter capacitor positive terminal to the common/
return terminal of the transformer secondary. Such a placement
will route high magnitude common mode surge currents away
from the TinySwitch-4 device. Note – if an input π (C, L, C) EMI
filter is used then the inductor in the filter should be placed
between the negative terminals of the input filter capacitors.
Optocoupler
Place the optocoupler physically close to the TinySwitch-4 to
minimizing the primary-side trace lengths. Keep the high
current, high-voltage drain and clamp traces away from the
optocoupler to prevent noise pick up.
Output Diode
For best performance, the area of the loop connecting the
secondary winding, the output diode and the output filter
capacitor, should be minimized. In addition, sufficient copper
area should be provided at the anode and cathode terminals of
the diode for heat sinking. A larger area is preferred at the quiet
cathode terminal. A large anode area can increase high
frequency radiated EMI.
PC Board Leakage Currents
TinySwitch-4 is designed to optimize energy efficiency across
the power range and particularly in standby/no-load conditions.
Current consumption has therefore been minimized to achieve
this performance. The ENABLE/UNDERVOLTAGE pin under-
voltage feature for example has a low threshold (~1
μA)
to
detect whether an undervoltage resistor is present.
Parasitic leakage currents into the ENABLE/UNDERVOLTAGE
pin are normally well below this 1
μA
threshold when PC board
assembly is in a well controlled production facility. However, high
humidity conditions together with board and/or package
contamination, either from no-clean flux or other contaminants,
can reduce the surface resistivity enough to allow parasitic
currents >1
μA
to flow into the ENABLE/UNDERVOLTAGE pin.
These currents can flow from higher voltage exposed solder
pads close to the ENABLE/UNDERVOLTAGE pin such as the
BYPASS/MULTI-FUNCTIONAL pin solder pad preventing the
design from starting up. Designs that make use of the
undervoltage lockout feature by connecting a resistor from the
high-voltage rail to the ENABLE/UNDERVOLTAGE pin are not
affected.
If the contamination levels in the PC board assembly facility are
unknown, the application is open frame or operates in a high
pollution degree environment and the design does not make
use of the undervoltage lockout feature, then an optional
390 kW resistor should be added from ENABLE/UNDERVOLTAGE
pin to SOURCE pin to ensure that the parasitic leakage current
into the ENABLE/UNDERVOLTAGE pin is well below 1
μA.
Note that typical values for surface insulation resistance (SIR)
where no-clean flux has been applied according to the
suppliers’ guidelines are >>10 MW and do not cause this issue.
11
www.powerint.com
Rev. A 09/12
POWERINT [ POWER INTEGRATIONS, INC. ]
