TOP221-227
VIN
VIN
DRAIN
0
VOUT
0
IOUT
0
1
2
8
1
2
8
1
VC(reset)
VC
0
•••
•••
1
2
8
1
2
8
1
IC
0
•••
1
2
•••
1
3
1
PI-2030-042397
Figure 6. Typical Waveforms for (1) Normal Operation, (2) Auto-restart, and (3) Power Down Reset.
the output MOSFET off until the start of the next clock cycle.
The current limit comparator threshold voltage is temperature
compensated to minimize variation of the effective peak current
limit due to temperature related changes in output MOSFET
R
DS(ON)
.
The leading edge blanking circuit inhibits the current limit
comparator for a short time after the output MOSFET is turned
on. The leading edge blanking time has been set so that current
spikes caused by primary-side capacitances and secondary-side
rectifier reverse recovery time will not cause premature
termination of the switching pulse.
The current limit can be lower for a short period after the leading
edge blanking time as shown in Figure 12. This is due to
dynamic characteristics of the MOSFET. To avoid triggering
the current limit in normal operation, the drain current waveform
should stay within the envelope shown.
Shutdown/Auto-restart
To minimize
TOPSwitch
power dissipation, the shutdown/
auto-restart circuit turns the power supply on and off at an auto-
restart duty cycle of typically 5% if an out of regulation
condition persists. Loss of regulation interrupts the external
current into the CONTROL pin. V
C
regulation changes from
shunt mode to the hysteretic auto-restart mode described above.
When the fault condition is removed, the power supply output
becomes regulated, V
C
regulation returns to shunt mode, and
normal operation of the power supply resumes.
Overtemperature Protection
Temperature protection is provided by a precision analog
circuit that turns the output MOSFET off when the junction
temperature exceeds the thermal shutdown temperature
(typically 135
°C).
Activating the power-up reset circuit by
removing and restoring input power or momentarily pulling the
CONTROL pin below the power-up reset threshold resets the
latch and allows
TOPSwitch
to resume normal power supply
operation. V
C
is regulated in hysteretic mode and a 4.7 V to
5.7 V (typical) sawtooth waveform is present on the CONTROL
pin when the power supply is latched off.
High-voltage Bias Current Source
This current source biases
TOPSwitch
from the DRAIN pin and
charges the CONTROL pin external capacitance (C
T
) during
start-up or hysteretic operation. Hysteretic operation occurs
during auto-restart and overtemperature latched shutdown.
The current source is switched on and off with an effective duty
cycle of approximately 35%. This duty cycle is determined by
the ratio of CONTROL pin charge (I
C
) and discharge currents
(I
CD1
and I
CD2
). This current source is turned off during normal
operation when the output MOSFET is switching.
C
12/97
5
POWERINT [ POWER INTEGRATIONS, INC. ]
