TOP252-262
Pin Functional Description
DRAIN (D) Pin:
High-voltage power MOSFET DRAIN pin. The internal start-up
bias current is drawn from this pin through a switched high-
voltage current source. Internal current limit sense point for
drain current.
CONTROL (C) Pin:
Error amplifier and feedback current input pin for duty cycle
control. Internal shunt regulator connection to provide internal
bias current during normal operation. It is also used as the
connection point for the supply bypass and auto-restart/
compensation capacitor.
EXTERNAL CURRENT LIMIT (X) Pin (Y, M, E and L package):
Input pin for external current limit adjustment and remote
ON/OFF. A connection to SOURCE pin disables all functions
on this pin.
VOLTAGE MONITOR (V) Pin (Y & M package only):
Input for OV, UV, line feed forward with DC
MAX
reduction, output
overvoltage protection (OVP), remote ON/OFF and device reset.
A connection to the SOURCE pin disables all functions on this pin.
MULTI-FUNCTION (M) Pin (P & G packages only):
This pin combines the functions of the VOLTAGE MONITOR (V)
and EXTERNAL CURRENT LIMIT (X) pins of the Y package into
one pin. Input pin for OV, UV, line feed forward with DC
MAX
PI-4711-021308
PI-4983-021308
+
R
LS
4M
V
UV
= I
UV
× R
LS
+ V
V
(I
V
= I
UV
)
V
OV
= I
OV
× R
LS
+ V
V
(I
V
= I
OV
)
For R
LS
= 4 M
V
UV
= 102.8 VDC
V
OV
= 451 VDC
DC
MAX
@100 VDC = 76%
DC
MAX
@375 VD
C = 41%
C
DC
Input
Voltage
D
V
CONTROL
S
X
R
IL
12 k
For R
IL
= 12 k
I
LIMIT
= 61%
See Figure 55b for
other resistor values
(R
IL
) to select different
I
LIMIT
values.
E Package (eSIP-7C)
Exposed Pad
(Hidden)
Internally
Connected to
SOURCE Pin
Y Package (TO-220-7C)
Note: Y package for TOP259-261
-
Figure 5.
TOP254-258 Y and All M/E/L Package Line Sense and Externally Set
Current Limit.
12345 7
VXCF S D
L Package (eSIP-7F)
Tab Internally
Connected to
SOURCE Pin
+
R
LS
4M
V
UV
= I
UV
× R
LS
+ V
V
(I
V
= I
UV
)
V
OV
= I
OV
× R
LS
+ V
V
(I
V
= I
OV
)
For R
LS
= 4 M
V
UV
= 102.8 VDC
V
OV
= 451 VDC
DC
MAX
@100 VDC = 76%
DC
MAX
@375 VD
C = 41%
C
12345 7
V XCSG D
Lead Bend
Outward from Drawing
(Refer to eSIP-7F Package
Outline Drawing)
DC
Input
Voltage
D
V
CONTROL
12345 7
VXCF S D
M Package
V
X
C
D
S
R
IL
12 k
X
G
For R
IL
= 12 k
I
LIMIT
= 61%
See Figure 55b for
other resistor values
(R
IL
) to select different
I
LIMIT
values.
Y Package (TO-220-7C)
10
S
9
8
7
6
S
S
S
S
Tab Internally
Connected to
SOURCE Pin
Note: Y package for TOP254-258
Figure 6.
-
1
2
3
5
TOP259-261 Y Package Line Sense and External Current Limit.
+
V
UV
= I
UV
× R
LS
+ V
M
(I
M
= I
UV
)
V
OV
= I
OV
× R
LS
+ V
M
(I
M
= I
OV
)
R
LS
DC
Input
Voltage
D
M
CONTROL
P and G Package
M
C
4M
1
2
8
7
6
S
S
S
S
For R
LS
= 4 M
V
UV
= 102.8 VDC
V
OV
= 451 VDC
DC
MAX
@100 VDC = 76%
DC
MAX
@375 VDC = 41%
D
4
5
12345 7
VXCS F D
PI-4644-091108
C
S
PI-4712-120307
-
Figure 7.
Figure 4.
Pin Configuration (Top View).
P/G Package Line Sense.
6
Rev. F 01/09
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