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PSOT15LC-LF-T7 参数 Datasheet PDF下载

PSOT15LC-LF-T7图片预览
型号: PSOT15LC-LF-T7
PDF下载: 下载PDF文件 查看货源
内容描述: 超低电容TVS阵列 [ULTRA LOW CAPACITANCE TVS ARRAY]
分类和应用: 电视
文件页数/大小: 5 页 / 67 K
品牌: PROTEC [ PROTEK DEVICES ]
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PSOT03LC  
thru  
PSOT36LC  
APPLICATION NOTE  
The PSOTxxLC Series are low capacitance TVS arrays designed to protect I/O or data lines from the damaging effects of ESD or EFT. This product  
series provides unidirectional & bidirectional protection, with a surge capability of 500 Watts PPP per line for an 8/20µs waveform and ESD protection  
> 40 kilovolts.  
BIDIRECTIONAL COMMON-MODE CONFIGRUATION (Figure 1)  
Figure 1 - Common-Mode I/O Port Protection  
Two PSOTxxLC devices, when used in paralell, provide protection in a  
common-mode configuration as depicted in Figure 1.  
I/O LINE  
Circuit connectivity is as follows:  
I/O Line is connected to Device 1, Pin 1.  
I/O Line is connect to Device 2, Pin 2.  
Device 1, Pin 2 is connected to ground.  
Device 2, Pin 1 is connected to ground.  
Device 1 & 2, Pin 3 is not connected.  
1
2
2
1
3
3
BIDIRECTIONAL DIFFERENTIAL-MODE CONFIGRUATION (Figure 1)  
In addition, two PSOTxxLC devices, when used in paralell, provide  
protection in a differential-mode configuration for Ethernet applications as  
depicted in Figure 2.  
Circuit connectivity is as follows:  
GND  
I/O Line 1 is connected to Device 1, Pin 1.  
I/O Line 1 is connect to Device 2, Pin 2.  
I/O Line 2 is connected to Device 1, Pin 1.  
I/O Line 2 is connect to Device 2, Pin 2.  
Device 1 & 2, Pin 3 is not connected.  
Figure 2 - Differential-Mode Ethernet Protection  
I/O 1  
CIRCUIT BOARD LAYOUT RECOMMENDATIONS  
Circuit board layout is critical for Electromagnetic  
Compatibility (EMC) protection. The following  
guidelines are recommended:  
1
2
2
1
3
3
The protection device should be placed near the  
input terminals or connectors, the device will  
divert the transient current immediately before it  
can be coupled into the nearby traces.  
I/O 2  
The path length between the TVS device and the  
protected line should be minimized.  
All conductive loops including power and ground  
loops should be minimized.  
The transient current return path to ground  
should be kept as short as possible to reduce  
parasitic inductance.  
Ground planes should be used whenever  
possible. For multilayer PCBs, use ground vias.  
05066.R6 3/07  
4
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