April 2008
rev 1.6
Pin Description
Pin Number
ASM705/706
DIP/
SO
1
ASM705/706/707/708
ASM813L
ASM707/708
DIP/
SO
1
ASM813L
DIP/
SO
1
Name
Function
MicroSO
MicroSO
MicroSO
MR
3
3
3
Manual reset input. The active LOW input
triggers a reset pulse. A 250 µA pull-up
current allows the pin to be driven by
TTL/CMOS logic or shorted to ground with a
switch.
+5V power supply input.
Ground reference for all signals.
Power-fail input voltage monitor. With PFI
less than 1.25V, PFO goes LOW. Connect
PFI to Ground or V
CC
when not in use.
Power-fail output. The output is active LOW
and sinks current when PFI is less than
1.25V.
Watchdog input. WDI controls the internal
watchdog timer. A HIGH or LOW signal for
1.6sec at WDI allows the internal timer to
run-out, setting WDO LOW. The watchdog
function is disabled by floating WDI or by
connecting WDI to a high impedance three-
state buffer. The internal watchdog timer
clears when: RESET is asserted; WDI is
three-stated ; or WDI sees a rising or falling
edge.
Not Connected.
Active LOW reset output. Pulses LOW for
200ms when triggered, and stays LOW
whenever V
CC
is below the reset threshold.
RESET remains LOW for 200ms after V
CC
rises above the reset threshold or MR goes
from LOW to HIGH. A watchdog timeout will
not trigger RESET unless WDO is
connected to MR.
Watchdog output. WDO goes LOW when
the 1.6 second internal watchdog timer
times-out and does not go HIGH until the
watchdog is cleared. In addition, when V
CC
falls below the reset threshold, WDO goes
LOW. Unlike RESET, WDO does not have a
minimum pulse width and as soon as V
CC
exceeds the reset threshold, WDO goes
HIGH with no delay.
Active HIGH reset output. The inverse of
RESET. The ASM813L only has a RESET
output.
2
3
4
5
4
5
6
7
2
3
4
5
4
5
6
7
2
3
4
5
4
5
6
7
V
CC
GND
PFI
PFO
6
8
-
-
6
8
WDI
-
-
6
8
-
-
NC
7
1
7
1
-
-
RESET
8
2
-
-
8
2
WDO
-
-
8
2
7
1
RESET
Low Power µP Supervisor Circuits
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
