ASM705/706/707/708
ASM813L
April 2008
rev 1.6
Pin Description
Pin Number
ASM707/708
ASM705/706
ASM813L
Name
Function
DIP/
DIP/
SO
DIP/
SO
MicroSO
SO
MicroSO
MicroSO
Manual reset input. The active LOW input
triggers a reset pulse. A 250 µA pull-up
current allows the pin to be driven by
TTL/CMOS logic or shorted to ground with a
switch.
MR
1
3
1
3
1
3
2
3
4
5
2
3
4
5
2
3
4
5
VCC
+5V power supply input.
GND
Ground reference for all signals.
Power-fail input voltage monitor. With PFI
less than 1.25V, PFO goes LOW. Connect
PFI to Ground or VCC when not in use.
Power-fail output. The output is active LOW
and sinks current when PFI is less than
1.25V.
4
5
6
7
4
5
6
7
4
5
6
7
PFI
PFO
Watchdog input. WDI controls the internal
watchdog timer. A HIGH or LOW signal for
1.6sec at WDI allows the internal timer to
run-out, setting WDO LOW. The watchdog
function is disabled by floating WDI or by
connecting WDI to a high impedance three-
state buffer. The internal watchdog timer
clears when: RESET is asserted; WDI is
three-stated ; or WDI sees a rising or falling
edge.
6
8
-
-
6
8
WDI
NC
-
-
6
7
8
1
-
-
-
-
Not Connected.
Active LOW reset output. Pulses LOW for
200ms when triggered, and stays LOW
whenever VCC is below the reset threshold.
RESET remains LOW for 200ms after VCC
7
1
RESET rises above the reset threshold or MR goes
from LOW to HIGH. A watchdog timeout will
not trigger RESET unless WDO is
connected to MR.
Watchdog output. WDO goes LOW when
the 1.6 second internal watchdog timer
times-out and does not go HIGH until the
watchdog is cleared. In addition, when VCC
8
-
2
-
-
-
8
7
2
1
WDO
falls below the reset threshold, WDO goes
LOW. Unlike RESET, WDO does not have a
minimum pulse width and as soon as VCC
exceeds the reset threshold, WDO goes
HIGH with no delay.
Active HIGH reset output. The inverse of
8
2
RESET RESET. The ASM813L only has a RESET
output.
Low Power µP Supervisor Circuits
3 of 15
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
