欢迎访问ic37.com |
会员登录 免费注册
发布采购

ASMP5P23S04A 参数 Datasheet PDF下载

ASMP5P23S04A图片预览
型号: ASMP5P23S04A
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V “ SpreadTrak ”零延迟缓冲器 [3.3V ‘SpreadTrak’ Zero Delay Buffer]
分类和应用:
文件页数/大小: 15 页 / 412 K
品牌: PULSECORE [ PulseCore Semiconductor ]
 浏览型号ASMP5P23S04A的Datasheet PDF文件第2页浏览型号ASMP5P23S04A的Datasheet PDF文件第3页浏览型号ASMP5P23S04A的Datasheet PDF文件第4页浏览型号ASMP5P23S04A的Datasheet PDF文件第5页浏览型号ASMP5P23S04A的Datasheet PDF文件第6页浏览型号ASMP5P23S04A的Datasheet PDF文件第7页浏览型号ASMP5P23S04A的Datasheet PDF文件第8页浏览型号ASMP5P23S04A的Datasheet PDF文件第9页  
November 2006
ASMP5P23S04A
3.3V ‘SpreadTrak’ Zero Delay Buffer
rev 1.4
Features
Zero input - output propagation delay, adjustable
by capacitive load on FBK input.
Multiple configurations - Refer “ASM5P23S04A
Configurations Table”.
Input frequency range: 15 MHz to 133 MHz
Multiple low-skew outputs.
Output-output skew less than 200 pS.
Device-device skew less than 500 pS.
Two banks of two outputs each.
Less than 200 pS cycle-to-cycle jitter
(-1, -1H, -2, -2H).
FBK pin, and can be obtained from one of the outputs. The
input-to-output propagation delay is guaranteed to be less
than 250 pS, and the output-to-output skew is guaranteed
to be less than 200 pS.
The ASM5P23S04A has two banks of two outputs each.
Multiple ASM5P23S04A devices can accept the same input
clock and distribute it. In this case the skew between the
outputs of the two devices is guaranteed to be less than
500 pS.
The
ASM5P23S04A
(Refer
is
available
in
two
different
Available in space saving, 8-pin 150-mil SOIC
package.
3.3V operation.
Advanced 0.35µ CMOS technology.
Industrial temperature available.
‘SpreadTrak’.
configurations
“ASM5P23S04A
Configurations
Table). The ASM5P23S04A-1 is the base part, where the
output frequencies equal the reference if there is no
counter in the feedback path. The ASM5P23S04A-1H is
the high-drive version of the -1 and the rise and fall times
on this device are much faster.
The ASM5P23S04A-2 allows the user to obtain Ref and
1/2X frequencies on each output bank. The exact
configuration and output frequencies depend on which
output drives the feedback pin.
The ASM5P23S04A-2H is a high-drive version with REF/2
on both banks.
Functional Description
ASM5P23S04A is a versatile, 3.3V zero-delay buffer
designed
to
distribute
high-speed
clocks
in
PC,
workstation, datacom, telecom and other high-performance
applications. It is available in a 8-pin package. The part has
an on-chip PLL, which locks to an input clock, presented on
the REF pin. The PLL feedback is required to be driven to
Block Diagram
FBK
CLKA1
REF
PLL
CLKA2
/2
Extra Divider (-2)
CLKB1
CLKB2
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.