November 2006
rev 0.2
P2010A
Pin Configuration
11
88
77
66
XIN/CLK
XOUT
2
2
SR0
P2040C
P2010A
ModOUT
3
3
5
5
4
4
SSON
Pin Description
Pin# Pin Name
Type
Description
1
XIN/CLK
I
Connect to crystal or externally generated clock signal.
2
XOUT
I
Connect to crystal. No connect if externally generated clock signal is used.
Digital logic input used to select Input Frequency Range (see Table 1).
3
4
5
6
7
8
FS0
VSS
I
P
I
This pin has an internal pull-up resistor.
Ground Connection. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active Low). Spread
SSON
ModOUT
SR0
Spectrum function enable when low. This pin has an internal pull-low resistor.
O
I
Spread Spectrum Clock Output.
Digital logic input used to select Spreading Range (see Table 1).
This pin has an internal pull-up resistor.
VDD
P
Connect to +3.3V or +5.0V
Table 1 - Spread Range Selection
FS0
SR0
Spreading Range
Input Frequency
Modulation rate
1
1
0
0
0
1
0
1
+/- 1.50%
+/- 2.50%
+/- 1.25%
+/- 2.00%
10MHz to 20MHz
10MHz to 20MHz
20MHz to 35MHz
20MHz to 35MHz
(Fin/10)*20.83KHz
(Fin/10)*20.83KHz
(Fin/10)*20.83KHz
(Fin/10)*20.83KHz
Low Frequency EMI Reduction IC
2 of 8
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
