November 2006
rev 1.3
LCD Panel EMI Reduction IC
Features
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FCC approved method of EMI attenuation.
Provides up to 20dB of EMI suppression.
Generates a low EMI spread spectrum clock of
the input frequency.
Input frequency range: 30MHz to 100MHz.
3.3v Operating Voltage
Optimized
Internal
for
loop
VGA,
filter
SVGA,
and
higher
external
resolution XGA LCD Panels.
minimizes
P2040A
modulator designed specifically for digital flat panel
applications.
The
P2040A
reduces
electromagnetic
interference (EMI) at the clock source, allowing system
wide reduction of EMI of down stream clock and data
dependent signals. The P2040A allows significant system
cost savings by reducing the number of circuit board
layers ferrite beads,
regulations.
The P2040A uses the most efficient and optimized
modulation profile approved by the FCC and is
implemented in a proprietary all digital method.
The P2040A modulates the output of a single PLL in
order to “spread” the bandwidth of a synthesized clock,
and more importantly, decreases the peak amplitudes of
its harmonics. This results in significantly lower system
EMI compared to the typical narrow band signal
graphic
accelerator
produced by oscillators and most frequency generators.
Lowering EMI by increasing a signal’s bandwidth is called
‘spread spectrum clock generation’.
shielding and other passive
components that are traditionally required to pass EMI
components and board space.
Six selectable high spread ranges up to ± 2%.
Two selectable modulation rates.
SSON# control pin for spread spectrum enable
and disable options.
Low cycle-to-cycle jitter.
Wide operating range.
Low power CMOS design.
Supports
most
mobile
specifications.
Products available for automotive temperature
range.
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(Refer
Spread
Spectrum
Range
Selection Tables)
Available in 8-pin SOIC and TSSOP Packages.
Applications
The P2040A is targeted towards digital flat panel
applications for notebook PCs, palm-size PCs, office
automation equipments and LCD monitors.
VDD
Product Description
The P2040A is a versatile spread spectrum frequency
Block Diagram
SR0 SR1 MRA SSON#
Modulation
CLKIN
Frequency
Divider
Feedback
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
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Tel: 408-879-9077
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Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
