November 2006
rev 0.2
Pin Configuration
P2041A
XIN/CLK
XOUT
SR1
VSS
1
1
2
2
33
4
4
8
8
7
7
6
6
5
5
VDD
SR0
ModOUT
SSON
P2041A
P2040C
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin Name
XIN/CLK
XOUT
SR1
VSS
SSON
ModOUT
SR0
VDD
Type
I
I
I
P
I
O
I
P
Description
Connect to crystal or externally generated clock signal.
Connect to crystal. No connect if externally generated clock signal is used.
Digital logic input used to select Spreading Range (see Table 1).
This pin has an internal pull-up resistor.
Ground Connection. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active Low). Spread
Spectrum function enable when low. This pin has an internal pull-low resistor.
Spread Spectrum Clock Output.
Digital logic input used to select Spreading Range (see Table 1).
This pin has an internal pull-up resistor.
Connect to +3.3V or +5.0V
Spread Range Selection
SR1
0
0
1
1
SR0
0
1
0
1
Spreading Range
+/- 1.50%
+/- 2.50%
+/- 0.50%
+/- 1.00%
Modulation rate
(Fin/40)*34.72 KHz
(Fin/40)*34.72 KHz
(Fin/40)*34.72 KHz
(Fin/40)*34.72 KHz
Versatile EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
