August 2007
rev 1.5
Pin Configuration
P2042A
CLKIN
1
CP0
2
8
VDD
7
SR0
P2042A
CP1
3
VSS
4
6
5
ModOUT
SSON#
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin
Name
CLKIN
CP0
CP1
VSS
SSON#
ModOUT
SR0
VDD
Type
I
I
I
P
I
O
I
P
Description
External reference frequency input. Connect to externally generated reference signal.
Digital logic input used to select charge pump current. This pin has an internal pull-up
resistor.
Refer Modulation Selection Table.
Digital logic input used to select charge pump current. This pin has an internal pull-up
resistor.
Refer Modulation Selection Table.
Ground to entire chip. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread
Spectrum function enabled when LOW, disabled when HIGH.
This pin has an internal pull-low resistor.
Spread spectrum clock output.
Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor.
Power supply for the entire chip
Modulation Selection
CP0
0
0
0
0
1
1
1
1
CP1
0
0
1
1
0
0
1
1
SR0
0
1
0
1
0
1
0
1
Spreading Range (±%)
32.5MHz
0.56
1.94
1.36
1.92
1.24
1.91
0.91
1.47
54MHz
1.05
1.68
1.05
1.68
0.81
1.29
0.45
0.71
65MHz
1.00
1.56
1.00
1.56
0.66
1.02
0.34
0.54
81MHz
0.98
1.48
0.92
1.48
0.40
0.74
0.05
0.36
108MHz
0.80
1.22
0.67
1.06
0.27
0.43
0.15
0.21
Modulation Rate
(KHz)
(FIN /40) * 62.49
KHz
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
