November 2006
rev 1.1
P2180 / 81 / 82 / 83 / 84
VDD
Block Diagram
SRS
PLL
Modulation
XIN
Crystal
Oscillator
Frequency
Divider
Output
VCO
Phase
Loop
Filter
XOUT
Divider
Detector
Feedback
ModOUT
VSS
Pin Diagram
1
XIN
1
XIN
NC
8
8
NC
NC
XOUT
NC
NC
2
2
7
6
5
7
6
5
P2180X
P2181X
P2183X
VSS
SRS
VDD
VSS
SRS
VDD
3
4
3
4
ModOUT
ModOUT
Pin Description
Pin#
Pin Name
Type
Description
Connect to externally generated clock signal or crystal.
1
2
3
XIN
NC
VSS
I
No connect.
Ground to entire chip.
P
I
Spread Range Select. Digital logic input used to select frequency deviation (Refer
4
SRS
Spread Deviation Selections Table). This pin has an internal pull-up resistor.
5
6
7
ModOUT
VDD
O
P
Spread spectrum low EMI output.
Connect to +3.3V.
No connect.
NC
8
NC
No connect.
8*
XOUT
O
Crystal connection.
* Available for P2183 and P2184 only.
Low EMI Clock for Mobile VGA
2 of 9
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
