September 2006
rev 0.3
Test Circuits and Waveforms
ENABLE
CONTROL
INPUT
t
PZL
OUTPUT
NORMALLY SWITCH
LOW CLOSED
t
PZH
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
1.5V
V
OL
V
OH
1.5V
t
PHZ
0.3V
V
OH
V
OL
t
PLZ
0.3V
DISABLE
3V
1.5V
0V
V
OH
V
OL
Package 2
OUTPUT
t
PLH2
Package 1
OUTPUT
t
SK(PP)
INPUT
t
PLH1
PCS2P3805E
3V
t
PHL1
1.5V
0V
V
OH
1.5V
V
OL
V
OH
1.5V
V
OL
t
SK(PP)
t
PHL2
t
SK(PP)
= | t
PLH2
- t
PLH1
| or | t
PHL2
- t
PHL1
|
Enable and Disable Times
Note: 1.
Diagram shown for input Control Enable-LOW and input Control
Disable-HIGH
Part-to- Part Skew
Note:
Part-to- Part Skew is for package and speed grade.
3V
INPUT
t
PLH
OUTPUT
t
R
t
F
t
PHL
2.0V
0.8V
1.5V
0V
V
OH
1.5V
V
OL
OUTPUT
t
SK(P)
= | t
PLH
- t
PLH
|
INPUT
t
PLH
t
PHL
3V
1.5V
0V
V
OH
1.5V
V
OL
Pulse Skew
Propagation Delay
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
