November 2006
rev 0.2
2.5V Single Data Rate1:5 Clock Buffer Terabuffer
PCS2P5T9050A
Features
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Optimized for 2.5V LVTTL
Guaranteed Low Skew < 25pS (max)
Very low duty cycle distortion< 300pS (max)
High speed propagation delay < 1.8nS. (max)
Up to 200MHz operation
Very low CMOS power levels
Hot Insert able and over-voltage tolerant inputs
1:5 fan-out buffer
2.5V Supply Voltage
Available in TSSOP Package
The PCS2P5T9050A 2.5V single data rate (SDR) clock
buffer is a single-ended input to five single-ended outputs
buffer built on advanced metal CMOS technology. The
SDR
clock
buffer
fan-out
from a single input to five
single-ended outputs reduces the loading on the preceding
driver and provides an efficient clock distribution network.
Multiple power and grounds reduce noise.
Applications:
PCS2P5T9050A is targeted towards Clock and signal
distribution applications.
Functional Description
Block Diagram
GL
G
OUTPUT
CONTROL
Q1
OUTPUT
CONTROL
A
OUTPUT
CONTROL
Q2
Q3
OUTPUT
CONTROL
Q4
OUTPUT
CONTROL
Q5
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
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Tel: 408-879-9077
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Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
