September 2006
rev 0.4
PCS2I99447
Table 5. DC Characteristics (VCC = 3.3V ± 5%, TA = -40°C to +85°C)
Symbol
VIH
Characteristics
Min
2.0
-0.3
2.4
Typ
Max
VCC + 0.3
0.8
Unit
V
V
Condition
LVCMOS
Input High Voltage
VIL
VOH
Input Low Voltage
Output High Voltage
LVCMOS
V
IOH = -24 mA1
0.55
0.30
V
IOL = 24 mA
VOL
Output Low Voltage
V
IOL = 12 mA
ZOUT
IIN
ICCQ
Output Impedance
17
W
mA
mA
Input Current2
±300
2.0
VIN = VCC or GND
All VCC Pins
Maximum Quiescent Supply Current3
Note: 1. The PCS2I99447 is capable of driving 50Ω transmission lines on the incident edge. Each output drives one 50Ω parallel terminated transmission line to
a termination voltage of VTT. Alternatively, the device drives up to two 50Ω series terminated transmission lines (for VCC=3.3V).
2. Inputs have pull-down or pull-up resistors affecting the input current.
3. ICCQ is the DC current consumption of the device with all outputs open and the input in its default state or open.
Table 6. AC Characteristics (VCC = 3.3V ± 5%, TA = -40°C to +85°C)1
Symbol
fref
fmax
fP,REF
tr, tf
tPLH/HL
tPLZ, HZ
tPZL, ZH
5Characteristics
Min
0
0
Typ
Max
350
350
Unit
MHz
MHz
nS
nS
nS
Condition
Input Frequency
Output Frequency
Reference Input Pulse Width
CCLK0, CCLK1 Input Rise/Fall Time
1.4
1.02
3.3
11
0.8 to 2.0V
Propagation Delay
Output Disable Time
Output Enable Time
CCLK0 or CCLK1 to any Q
1.3
nS
nS
11
tS
tH
0.0
1.0
nS
nS
Setup Time
Hold Time
CCLK0 or CCLK1 to CLK_STOP3
CCLK0 or CCLK1 to CLK_STOP3
tsk(O)
tsk(PP)
Output-to-Output Skew
Device-to-Device Skew
150
2.0
pS
nS
Output Pulse Skew4
Output Duty Cycle
MHz
tSK(P)
DCQ
300
55
pS
%
fQ<170
45
50
DCREF = 50%
0.55 to 2.4V
tr, tf
tJIT(CC)
Output Rise/Fall Time
Cycle-to-cycle jitter
0.1
1.0
nS
pS
TBD
RMS (1σ)
Note: 1. AC characteristics apply for parallel output termination of 50Ω to VTT
.
2. Violation of the 1.0 nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
output duty cycle and maximum frequency specifications.
3. Setup and hold times are referenced to the falling edge of the selected clock signal input.
4. Output pulse skew is the absolute difference of the propagation delay times: | tPLH - tPHL |.
3.3V/2.5V 1:9 LVCMOS Clock Fanout Buffer
4 of 14
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
