September 2006
rev 0.4
PCS2I99448
Table 1. FUNCTION TABLE
Control
CLK_SEL
OE
Default
0
1
1
1
PECL differential input selected
CCLK input selected
Outputs enabled
Outputs disabled (high-impedance state)1
Outputs synchronously stopped in logic low
state
1
Outputs active
CLK_STOP
Note: 1. OE=0 will high-impedance tristate all outputs independent on CLK_STOP.
Table 2. PIN CONFIGURATION
Pin#
Pin Name
I/O
Type
Function
4,3
Input
LVPECL LVPECL Clock Inputs
PCLK, PCLK
CCLK
2
1
Input
Input
LVCMOS Alternative clock signal input
LVCMOS Clock input select
CLK_SEL
5
6
Input
LVCMOS Clock output enable/disable
CLK_STOP
OE
Output enable/disable
LVCMOS
Input
Output
Supply
(high–impedance tristate)
31,29,27,25,23,21,19,17,15,13,11,9 Q0 – Q11
LVCMOS Clock output
Negative power supply (GND) for
8,12,16,20,24,28,32
GND
Ground
I/O and core.
Positive power supply for I/O and
core. All VCC pins must be
7,10,14,18,22,26,30
VCC
Supply
VCC
connected to the positive power
supply for correct operation
Table 3. ABSOLUTE MAXIMUM RATINGS1
Symbol
Parameter
Min
-0.3
-0.3
-0.3
Max
3.9
Unit
V
Supply Voltage
VCC
VIN
DC Input Voltage
DC Output Voltage
DC Input Current
DC Output Current
V
VCC + 0.3
V
VOUT
IIN
VCC + 0.3
±20
mA
mA
°C
±50
125
IOUT
TStor
Storage Temperature Range
-65
Note: 1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
3 of 15
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
