September 2006
rev 0.4
PCLK
PCLK
V
PP
V
CMR
CCLK
PCS2I99448
V
CC
V
CC
÷2
GND
V
CC
V
CC
÷2
Q
X
t
P(LH)
t
P(HL)
V
CC
V
CC
÷2
GND
Q
X
t
P(LH)
t
P(HL)
GND
Figure 11. Propagation Delay (t
PD
) Test Reference
V
CC
V
CC
÷2
GND
V
CC
V
CC
÷2
t
SK(LH)
t
SK(HL)
GND
Q
X
CCLK
Figure 12. Propagation Delay (t
PD
) Test Reference
V
CC
V
CC
÷2
GND
V
CC
V
CC
÷2
t
P(LH)
t
P(HL)
t
SK(P)
=| t
PHL
- t
PHL
|
GND
The pin-to-pin skew is defined as the worst case
difference in propagation between any similar delay path
within a single device
Figure 14. Output Pulse Skew (t
SK(P)
Test Reference
Figure 13. Output–to–Output Skew t
SK(LH, HL)
V
CC
V
CC
÷2
GND
t
P
T
0
DC (t
P
÷T
0
Χ
100%)
t
F
t
R
V
CC
= 3.3V V
CC
= 2.5V
2.4
0.5
1.8V
0.6V
Figure 16. Output Transition Time Test Reference
The time from the output controlled edge to the
non-controlled edge, divided by the time output
controlled edge, expressed as a percentage.
Figure 15. Output Duty Cycle (DC)
CCLK
PCLK
V
CC
V
CC
÷2
GND
T
JIT(CC)
= |T
N
-T
N
+ 1|
T
N
T
N
+ 1
V
CC
CLK_STOP
t
S
t
H
V
CC
÷2
GND
The variation in cycle time of a single between adjacent
cycles, over a random sample of adjacent cycle pairs
Figure 17. Cycle–to–Cycle Jitter Reference
Figure 18. Setup and Hold Time (t
S
, t
H
) Test
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
