September 2006
rev 0.3
2.5V CMOS Dual 1-To-5 Clock Driver
Features
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Advanced CMOS Technology
Guaranteed low skew < 200pS (max.)
Very low propagation delay < 2.5nS (max)
Very low duty cycle distortion < 270pS (max)
Very low CMOS power levels
Operating frequency up to 166MHz
TTL compatible inputs and outputs
Two independent output banks with 3-state control
1:5 fanout per bank
"Heartbeat" monitor output
V
CC
= 2.5V ± 0.2V
Available in SSOP and QSOP packages
PCS2P20805A
Functional Description
The PCS2P20805A is a 2.5V Clock driver built using
advanced CMOS technology. The device consists of two
banks of drivers, each with a 1:5 fanout and its own output
enable control. The device has a "heartbeat" monitor for
diagnostics and PLL driving. The MON output is identical to
all other outputs and complies with the output specifications
in
this
document.
The
PCS2P20805A
offers
low
capacitance inputs. The PCS2P20805A is designed for
high speed clock distribution where signal quality and skew
are critical. The PCS2P20805A also allows single point-to-
point transmission line driving in applications such as
address distribution, where one signal must be distributed
to multiple receivers with low skew and high signal quality.
Block Diagram
Pin Diagram
V
CCA
1
2
3
4
5
6
7
8
9
10
SSOP/ QSOP PACKAGE
TOP VIEW
20
19
18
17
V
CCB
OB
1
OB
2
OB
3
GND
B
OB
4
OB
5
MON
OE
B
IN
B
OE
A
IN
A
5
OA
1
– OA
5
OA
1
OA
2
OA
3
GND
A
PCS2P20805A
16
15
14
13
12
11
IN
B
OE
B
5
OB
1
– OB
5
OA
4
OA
5
GND
Q
MON
OE
A
IN
A
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200 Campbell, CA 95008
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Tel: 408-879-9077
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Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
