September 2006
rev 0.3
Test Circuits and Waveforms
V
CC
6V
PCS2P3805E
Open
GND
500Ω
V
IN
Pulse
Generator
R
T
D.U.T
R
L
V
OUT
C
L
500Ω
Enable and Disable Time Circuit
V
CC
INPUT
t
PLH1
V
IN
Pulse
Generator
R
T
D.U.T
R
L
V
OUT
C
L
OUTPUT 2
t
PLH2
t
PHL2
OUTPUT 1
t
SK(O)
t
SK(O)
t
PHL1
3V
1.5V
0V
V
OH
1.5V
V
OL
V
OH
1.5V
V
OL
t
SK(O)
= | t
PLH2
- t
PLH1
| or | t
PHL2
- t
PHL1
|
C
L
= 15pF Test Circuit
Output Skew – t
SK(o)
Switch Position
Test
Disable Low
Enable Low
Disable High
Enable High
Test Conditions
Switch
6V
GND
Symbol
C
L
R
T
R
L
t
R
/ t
F
Definitions:
V
CC
= 3.3V ±0.3V
15
Z
OUT
of pulse generator
33
1 (0V to 3V or 3V to 0V)
Unit
pF
Ω
Ω
nS
C
L
= Load capacitance: includes jig and probe capacitance.
R
T
= Termination resistance: should be equal to
Z
OUT
of the Pulse
Generator.
t
R
/ t
F
= Rise/Fall time of the input stimulus from the Pulse Generator.
3.3V CMOS Dual 1-To-5 Clock Driver
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
