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PCS2P2310ANZG-28-AT 参数 Datasheet PDF下载

PCS2P2310ANZG-28-AT图片预览
型号: PCS2P2310ANZG-28-AT
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V的SDRAM缓冲区用于移动PC与4 SO- DIMMsQ [3.3V SDRAM Buffer for Mobile PCS with 4 SO-DIMMsQ]
分类和应用: 存储内存集成电路光电二极管过程控制系统动态存储器PCS
文件页数/大小: 12 页 / 502 K
品牌: PULSECORE [ PulseCore Semiconductor ]
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September 2006
rev 0.5
PCS2I2310ANZ
3.3V SDRAM Buffer for Mobile PCS with 4 SO-DIMMs
Features
One input to 10 output buffer/driver
Supports up to four SDRAM SO-DIMMs
Two additional outputs for feedback
Serial interface for output control
Low skew outputs
Up to 133MHz operation
Multiple V
DD
and V
SS
pins for noise reduction
Dedicated OE pin for testing
Space-saving 28 Pin SSOP package
3.3V operation
Functional Description
The PCS2I2310ANZ is a 3.3V buffer designed to distribute
high-speed clocks in mobile PC applications. The part has
10 outputs, 8 of which can be used to drive up to four
SDRAM SO-DIMMs, and the remaining can be used for
external feedback to a PLL. The device operates at 3.3V
and outputs can run up to 133MHz, thus making it
compatible with Pentium II
®
processors.
The PCS2I2310ANZ also includes a serial interface (IIC),
which can enable or disable each output clock. The IIC is
Slave Receiver only and is Standard mode compliant. IIC
Master can write into the IIC registers but cannot read
back. The first two bytes after address should be ignored
by IIC Block and data is valid after these two bytes as given
in IIC Byte Flow Table. On power-up, all output clocks are
enabled. A separate Output Enable pin facilitates testing on
ATE.
i
i
Pentium II is a registered trademark of Intel Corporation
Block Diagram
BUF_IN
SDRAM0
SDRAM1
SDRAM2
SDATA
Serial Interface
Decoding
SCLOCK
SDRAM3
SDRAM4
SDRAM5
SDRAM6
SDRAM7
SDRAM8
SDRAM9
OE
PulseCore Semiconductor Corporation
1715 S. Bascom Ave Suite 200, Campbell, CA 95008
Tel: 408-879-9077
Fax: 408-879-9018
www.pulsecoresemi.com
Notice: The information in this document is subject to change without notice.